tl;dr included at the bottom.

Suppose we have two logical buffers from different logic families, where buffer A drives buffer B. Buffer A has the following voltage thresholds: \$V_{OH}=8\ V\$, \$V_{IH}=6\ V\$, \$V_{IL}=4\ V\$, \$V_{OL}=2\ V\$; thus buffer A interprets all received voltages up to 4 V as a logical 0 and all received voltages above 6 B as a logical 1.

Suppose that the thresholds for buffer B are the same as that of A with the exception that B's \$V_{IL}=4.5\ V\$. This means that for all received voltages which A would interpret as valid logical 0, B also interprets as logical 0. According to my textbook (Foundations of Analog and Digital Circuits by Agarwal and Lang) this means that devices from B's logic family can be used with devices from A's logic family, since B guarantees that whenever A sends a valid signal, B will send a valid output; and that B will interpret as valid all the signals which A would interpret as valid.

So then there is this range of voltages \$ 4 < V_{received} < 4.5 \$ which is interpreted as valid logical 0 by B but would be considered invalid by A. I can see that since B's noise margin for logical 0s is bigger than A's, that B is in this respect an improvement over A, since if A sends a 0 which is received as 4.25 volts, B will still be able to interpret it as 0 whereas an A receiver would consider it invalid.

But it also seems that B's higher \$V_{IL}\$ means it could make more mistakes of the kind where A sends a logical 1 which through (a lot of) noise is received as 4.25 volts. An A receiver would consider this invalid but B will consider it a valid logical 0, when really it was a valid logical 1, so B propagates an incorrect bit.

So the bottom line is, do we just have to accept that fact that some types of errors will be more common when mixing logic families as long as valid signals will be handled correctly, or am I misinterpreting something?


1 Answer 1


tl; dr: you design for the worst-case noise margin as a composite of all your logic types, so that all the receivers will interpret logic low and high correctly.

To arrive at a set of levels that will work system-wide, you take your highest Vi(h) and lowest Vi(l), add some margin on top of each, and that defines your levels your driver must support.

Example: 5V HCMOS vs. 5V LSTTL:

  • HCMOS Vi(h)/Vi(l): 3.5 / 1.0V (0.7 / 0.2 VCC)
  • LSTTL Vi(h)/Vi(l): 2.0 / 0.8V

So taking the min Vi(l) and max Vi(h), we have:

  • composite system Vi(h)/Vi(l) = 3.5 / 0.8V

Add 100mV noise margin:

  • margined system Vi(h)/Vi(l) = 3.6 / 0.7V

So your system signal driver must be able to swing 0.7V for low and 3.6V for high to achieve 100mV of noise margin. In this case, HCMOS output can do that, while an LSTTL output cannot, at least not without the help of an external pull-up resistor as its Vo(h)(min) is only about 2.4V.

The threshold analysis is similar regardless of the logic types being mixed - or even if they're not being mixed at all but nevertheless have large fan-out loading to be considered (a big problem with TTL, less so with CMOS.)

If, for some reason, a mixed-logic system can't find a workable composite set of thresholds, a technique called level translation can be used to convert the output levels of one logic type to a set of reliable input thresholds for another.

Between using Vi(h)/Vi(l) analysis as shown, and level translation where necessary, there is never a cause to have a system where a signal's level is interpreted incorrectly by a receiver, ever. This is basic to a reliable logic design.

  • \$\begingroup\$ Thank you for the additional explanation; I see what you were saying before. I think the last thing I'm confused about is how do you enforce the new constraints on the devices when you're using them together? For example, if you get some HCMOS devices and some LSTTL devices and put them together, what physical changes in the system are you making to ensure that the system overall behaves as you've described here? Since otherwise it seems that each device will still just operate according to its own static discipline. \$\endgroup\$
    – Halleff
    May 30, 2020 at 22:39
  • \$\begingroup\$ It’s all about making sure each receiver sees the voltages they need to properly resolve a ‘1’ or a ‘0’. This gets challenging when mixing voltage domains, hence the need for level translators at times. \$\endgroup\$ May 31, 2020 at 3:19

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