enter image description here

I am trying to work out what function the components in inverter colors serve, this is a schematic I have derived from a net-list to make it easier to explain my answer

E1 is an Error amplifier inside a LDO Regulator (VCVS)

Net 3 is connected to source of a P-Channel MOSFET with upper and lower clips. (I think this is unusual as I have found that the output of error amplifier is with respect to the input)

Net 9 is the FB (Feedback) node,

Net 12is the reference voltage node,

2.8V output voltage is set using feedback resistive divider. Has dropout voltage of 220mV for 150mA. Nominal input is 3-5.5v.

Is there a name or key word for this type of compensation?

How does this help for stability, PSRR (both) e.g. If I wanted to perform open and closed loop analysis for placement of poles and zeros ? What would this change?

  • \$\begingroup\$ Presumably you drew the "unknown" circuit so, why did you draw it that way? \$\endgroup\$
    – Andy aka
    May 30, 2020 at 11:49
  • \$\begingroup\$ Its netlist derived schematic. And PSRR, load, line, regulation , transients matches currently it matches with datasheet. \$\endgroup\$
    – Pai
    May 30, 2020 at 11:50
  • \$\begingroup\$ I would recommend you redraw that schematic a little, e.g. in normal op amp symbols, I have a suspicion that E2 is a "buffer", but I am unfamiliar with this style, For E1, it seems flipping it and drawing a line on net 3 between E1/E2 would clear things up, for node 12, you might draw a voltage source, equally if there is a P-mosfet include it, \$\endgroup\$
    – Reroute
    May 30, 2020 at 12:54
  • \$\begingroup\$ As to my thoughts towards the answer, it looks to be some kind of AC gain / attenuation, but without a clearer schematic, I am a bit lost \$\endgroup\$
    – Reroute
    May 30, 2020 at 12:55
  • \$\begingroup\$ @Reroute have edited for better understanding, E2 is upper clip. \$\endgroup\$
    – Pai
    May 30, 2020 at 14:06

1 Answer 1


Those are frequency-compensation networks, so the LDO does not oscillate.

I've also seen such networks (implemented with long_channel FETs, etc) on the feedback path from the voltage divider.


Notice the 10K ohm on the error_amp output. Those 3 RCs turn on, and STAY ON, as the frequency increases.

Fundamentally you have a variable_ratio voltage divider, using 3 shunting networks.

And don't forget the 10Kohm also has to charge and discharge the gate capacitance of the series_regulation FET.

how to analyze it ? basically, you want a CLOSED LOOP with little or no ringing. Hence you could run a closed_loop response 1Hertz to 10,000,000 Hz, with 10 steps per decade, and look for peaking (indicating ringing).

And you could perform a TRANSIENT load_step of 50%, or a Vin step of 1 volt, and check for little or no ringing even at parameter extremes.

But you should also run an open_loop response, so you get to correlate ALL these various methods and learn some of the theory and the practicality.

One way to run the open_loop was what I showed a switch_reg designer many decades ago. He ended up with the world record for the most personally_designed "boxes" in orbit around the earth {best wishes, Pat}. His employer threw up hundreds of scientific satellites over the last 40 years, and I'd like to think his use of this trick helped keep him happily employed til he retired.

The trick --- see that feedback voltage divider? place a very large capacitor on the output. Now use a much smaller capacitor to inject some swept_sin at your choice of node.

  • \$\begingroup\$ How should I theoretically analyse it? Open loop analysis? Or can I understand which type of compensation from any datasheet plots? \$\endgroup\$
    – Pai
    May 30, 2020 at 17:30

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge that you have read and understand our privacy policy and code of conduct.

Not the answer you're looking for? Browse other questions tagged or ask your own question.