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I'm designing a D_FF from JK_FF.

The circuit I'm implementing is , as shown in the figure :-

enter image description here

Verilog Module Code :-

`timescale 1ns / 1ps

/* Conversion of a JK Flip Flop to a D Flip Flop 
    Connections are "J = D" and "K = ~D"  
*/


module d_ff_from_jk_ff (q,qbar,rst,clk,d);
        output reg q;
        output qbar;
      input rst, clk;
      input d;


 wire d_n;              // Inverted version of D input //
 assign d_n = ~d ;  

 jk_ff d_converted(q,qbar,clk,rst,d,d_n);

endmodule


/******************************************* JK Filp FLop Module ************************************/

 module jk_ff(q,qbar,clk,rst,j,k);
          output reg q;
          output qbar;
          input clk, rst;
          input j,k;

          assign qbar = ~q;

always @(posedge clk)
    begin
          if (rst) q<=1'b0;             // Synchronous Reset //

          else
            case ({j, k})

                2'b00: q<=q;            // Previous Value //
                2'b01: q<=1'b0;     
                2'b10: q<=1'b1;     
                2'b11: q<=~q;           // Toggle //
         endcase
end
endmodule 

Testbench Code :-

`timescale 1ns / 1ps


module testbench;

    // Inputs
    reg rst;
    reg clk;
    reg d;

    // Outputs
    wire q;
    wire qbar;

    // Instantiate the Unit Under Test (UUT)
    d_ff_from_jk_ff uut (
        .q(q), 
        .qbar(qbar), 
        .rst(rst), 
        .clk(clk), 
        .d(d)
    );

    initial begin
    clk = 1'b0;
    rst = 1'b1;


#10  rst=1'b0;

end


always #5 clk=~clk;

    initial begin

        d = 1;
        #50;
        d = 0;
        #50;
        d = 1;
        #50;
        d = 0;
        #50;

#100 $finish;

    end


endmodule

In the simulation output, the value of Qbar is changing as expected, but the waveform of Q is constantly held at a "X" (don't care) condition.

enter image description here

Can anyone tell me where I've gone wrong and what correction is to be made ?

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1 Answer 1

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I get a compile error with Cadence. In d_ff_from_jk_ff, change:

    output reg q;

to:

    output q;

After I fix that, q is only X for the first 5ns, then I see it toggle between 0 and 1 thereafter.

Here is the error I got:

 jk_ff d_converted(q,qbar,clk,rst,d,d_n);
                   |
xmelab: *E,RANOTL : A reg is not a legal lvalue in this context [6.1.2(IEEE)].
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  • \$\begingroup\$ This changed worked and I got the ouput Q. But without the change, with the same code as above , I was able to get the output when I used EDA Playground online . So is this got something to do with the simulator tool ? \$\endgroup\$ May 31, 2020 at 14:26
  • 2
    \$\begingroup\$ @AbhishekChunduri: Yes, as we've seen, different simulators sometimes produce different results. I 1st tried with SystemVerilog (IEEE 1800) enabled on my versions of VCS and Cadence, and I didn't even get warnings. And I didn't see the X you saw. So I defaulted back to IEEE 1364 mode, and then I saw compile errors on both simulators. \$\endgroup\$
    – toolic
    May 31, 2020 at 14:30

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