I'm looking at the following three data sheets for 74LS138 devices:

Each has a "switching characteristics" table giving propagation delay, and each table has two figures for each delay, for 2 and 3 "levels of delay." For example, here are the select-to-output delays (in nanoseconds) for each of the above:

            Levels   Low→High    High→Low
   Vendor  of Delay  Typ  Max    Typ  Max

TI ('138)      2     11   20     18   41
               3     21   27     20   39

 Motorola      2     13   20     27   41
               3     18   27     26   39

Fairchild      2     18   27     27   40
               3     18   27     27   40

For my purposes (address decoding logic for 8-bit CPUs) the high→low figure is the one of interest, and those are so close that it seems to make little difference. But I'm curious as to what these "Levels of Delay" are and why they make a difference to the Low to High timings on some versions of this device. And why does the TI SN74HCT138 not have these different levels of delay?


This refers to the number of gates that the signal passes through to affect the output.

The logic diagram below is useful here.

LS138 Logic Diagram

Looking at the path from SELECT A to Y0, the signal passes through 2 gates to affect the output; if I look at the path from SELECT A to Y5 the signal passes thrpough 3 gates.

So the first example has 2 levels of delay and the second has 3 levels of delay.


This diagram is from the TI data sheet:

enter image description here

Note that from input to output, there might be 2 or 3 logic functions (inversion, nand gate, etc) in the path. The more functions in the path the longer the delay. So I think the 2 level delay would be for a path like A, B, or C to Y0, while a 3-level delay would apply to a path like A to Y5, or G1 to any of the outputs.

As to why the HCT138 doesn't have multiple levels of delay, it's probably because of a desire to simplify the data sheet so that the delay values are all for the longest paths.

IMO, if someone were taking advantage of a 2-level delay vs a 3-level delay to meet timing, then their design was probably marginal anyway, at best.


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