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I have some RFSoc Evaluation Kit with 12-bit DACs and ADCs that support nearly 4 GSPS

I found out that sampling rate is related to bandwidth.

From experiment, I found out that this board's DAC and ADC center frequency upper limit is about 1 GHz.

I wonder what factor would affect the upper bound of the DAC and ADC center frequency.

I used to doing research on signal processing and is new to electric. Can someone please help me or provide some idea. Thanks in advance.

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The "center frequency upper limit" as you call it (the manufacturers simply refer to this as "analog bandwidth") is determined by the analog side of the ADC or DAC. This would include any filters, buffer amplifiers, and sample/hold circuits, as well as the characteristics of the internal and external wiring.

Accurate operation at high frequencies requires careful attention to a lot of details, because transmission-line effects come into play at smaller scales.

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