The Basys 3 advertises "internal clock speeds exceeding 450 MHz," but the default clock pin is connected to a 100MHz oscillator. Is it possible to configure the Basys 3 to use a 450MHz clock?
The circuits on the board have internal PLLs. These are blocks that can generate a signal (like a clock) that is related to the reference (in this case the reference is the 100 MHz oscillator), but not necessarily equal. There are various ways to implement these blocks, but almost all big digital circuits will contain one (or more) to create clocks based off a reference.
One of the benefits is that a PLL can usually change the ratio between the generated signal and the reference. This means you can use a single, fixed reference, yet still change your clock speed of the digital circuit (for example to achieve lower power)
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450 MHz is a pretty fast clock for an FPGA.
Yes, but only for a localized area of the FPGA; think interacting with outside devices that operate at higher speeds (HDMI, DDR3, ADCs, etc). Once the data is taken from the external devices and the information is within the FPGA then the clock rate should be brought down to something more reasonable for the FPGA like 100MHz.
100MHz may not seem fast when compared to something like a GHz processors but you would be surprised with how much can be done when an FPGA doesn't have an operating system to deal with or the limited number of cores that software designers are constrained to.
Not so TLDR explanation... I mean Yak Shaving Long (arguably off topic):
You may already know this but for people who are just getting started here is some background concerning why that "internal clock speed 450MHz" should have a really big asterisk by it.
High level Differences between an ASIC (silicon IC like a CPU) and an FPGA:
1. FPGAs use lookup tables to implement logic, at least Xilinx FPGAs do, while the logic on an ASIC, such as a CPU, is etched directly into silicon using transistor based logic (much faster).
A lookup table within the FPGA looks like the lookup table in a Digital Circuits 101 course:
2 input AND Gate: Address 00 = 0 Address 01 = 0 Address 10 = 0 Address 11 = 1
Where each bit of the address corresponds to an input of the AND gate. If I recall correctly, Artix 7 have 6 input LUTs so they can implement a logic gate that uses 6 inputs instead of just 2. I just opened up an implemented design and took a screen shot of a logic gate representation:
An AND gate inside of an ASIC, on the other hand, is etched into the silicon (and other metal layers) using multiple transistors in clever configurations: Look at this awesome 4 NAND gate IC!. The nice thing about etching the logic into the silicon and metal is that the designers can customize how the logic gate is implemented so that it is faster or takes up less power and/or area.
So while the designers of ASICs can customize how every single logic gate is instantiated to optimize for power and speed. FPGAs have a set number of look up tables that cannot be physically adjusted, so the speed limit is set in this respect.
2. A similar discussion relating to in chip memory (registers) and routing between logic cells on an FPGA vs an ASIC can be had.
Essentially because ASIC designers have so much control over every aspect of the design ASICs, generally, can be clocked at a higher frequency than an FPGA.
How the clock frequency is determined for FPGAs
Due to the re-programmable nature of an FPGA every time you generate an image the FPGA tool needs to analyze the timing. One aspect of this process is looking at the generated hardware to determine the longest time it takes for every branch of your logic to be actualized. Say that the synthesizer took your Verilog or VHDL and generated a logic structure that looks like this:
((!A & B) ^ C) or the 'not of A anded with B then the result of this ored with C'
Without considering optimization the following steps to implement this would be:
Awould need to be inverted taking up one lookup table
inverted Awould then need to be 'anded' with
Btaking up a second lookup table
- The result of the 'and' would then need to be 'ored' with
Cfinally taking up a third lookup table
The longest 'path' is the
A, it needs to go through three steps, while the
C only needs to go through one.
When the FPGA tools generate a bit file to download on your FPGA you can (and should) request a timing analysis.
The timing analysis will check to see how long it takes to complete
((!A & B) ^ C) logic equation. If the clock frequency you request is too fast for the equation to complete within one clock cycle you will fail timing and come out with a 'negative slack'. This means the FPGA cannot keep up and you will need to slow your clock frequency down or perform other optimizations.
When placing and routing is done within the FPGA the tools will take into consideration what frequency you may want to run and perform various optimizations to accomplish that but sometimes it just can't.
Asterisk time: Why can it 'run' at 450MHz?
Here is an image of a region within an FPGA
There are specialized circuits near the periphery (Left side of the image) of the FPGA to enable communication with external devices such as DDR3, ADCs or even HDMI. These portions of the FPGA are not as generic as the rest, they are not made to perform logic, or if so, very limited logic, a lot of these portions of the FPGAs look more like ASICs than they do FPGAs. These portions can run at higher frequencies.
You will notice that there is a line of red BRAMs after a small area of logic cells. This is set up so that users can cross clock boundaries (High frequency periphery interfaces with lower frequency general logic).
You will also notice that there is a small set of circuits in the middle of the periphery circuitry (orange), there are clocks interfaces, their intended purpose is for use with high speed external devices. They may be connected with external clocks that drive periphery circuits and logic.