Background info: I am using a 4 layer PCB stack: Signal, Gnd, Signal+Power, Signal (mostly ground). To avoid out of question issues, I use this set-up due to a reference design on Texas Instruments as they use the stack-up in the same format.

All the unused areas are ground on this PCB, I also use via stitching on the edges and on the signal traces.

My question is that, is it better to be generous on the ground vias where no signal or power traces are used or is it better to keep them as solid as possible? (please note that un-used areas are ground only on all layers).

I read some articles as ground via can be a noise source, some articles says it is good to use for EMC/EMI. Can anyone please explain what are the general good practice to use the ground vias for the un-used areas? It'd be also interesting to learn how to use the un-used ground areas on 2 layer PCB (ground vias or solid area)?

I am sharing a part of the PCB (no ground pour on the picture to see the vias better)

enter image description here

  • \$\begingroup\$ Are you stitching ground planes for reduced susceptibility of EMI? What frequency? That looks like way more vias than needed, except for maybe 6GHz. \$\endgroup\$
    – rdtsc
    Jun 3, 2020 at 12:58
  • \$\begingroup\$ yes, I am stitching for EMI/EMC although I haven't done any pre-test, but I assume it'd not hurt on the edges. I was wondering how about the vias on the other area (e.g., right side of the picture), would it have a positive effect on the PCB (EMI/EMC, better return paths, ..) or would it be a negative thing (noise source, cross talk, ..)? As I read so far, it looks like it'd not hurt to use it like this, one of the post says use more vias if you need to lower the inductance, but how do I know if I'd need it or not? I don't have too high frequencies on the PCB. I have a 868 MHz RF module. \$\endgroup\$
    – Angs
    Jun 3, 2020 at 13:12

1 Answer 1


Essentially via stitches only need to be spaced at about 1/20th of the minimum wavelength.

$$\lambda v = c$$ $$\lambda = \frac{c}{v}$$ $$v = \frac{c}{\lambda}$$

Where λ (lambda) is wavelength, v is frequency, and c is the speed of light.

\$\frac{300\text{Mm/s (speed of light)}}{868\text{MHz (/s)}}\$ is a wavelength of 0.3456m. A twenty-eth of that is 17.2cm. So with vias spaced at 17cm and significant ground copper, the top surface would appear almost completely reflective at 868MHz. Excessive vias can incur extra costs from the board manufacturer as the tiny drills wear out rather quickly and/or break, leading to rejects. For a few boards they may not care, but they will for many boards.

Would [stitching] have a positive effect on the PCB (EMI/EMC, better return paths, ..) or would it be a negative thing (noise source, cross talk, ..)?

This is a huge question. Generally, if you have an RF transmitter on the board, the same-side external copper (pour) should be ground, with stitching as above. Most modules have a "keepout" section where nothing should be below it - stitch both sides to ground around that area. If in or near a reflective source (such as in a metal box, on a metal table, etc.) it may be necessary to ground-pour the reverse side also. It's okay to run a few traces on top/bottom, but remember the wavelength - a blatantly exposed trace which is 17cm long will start to behave like an antenna at 868MHz.

If using a trace to connect an SMA or antenna to the RF module, all kinds of special requirements are needed such as impedance matching (width, thickness, and distance of trace to ground, possibly impedance matching components also), mitered corners, ground stitching around the entire trace, etc.) Take a look at The Signal Path for examples of very high frequency design and the details involved.

As for EMC, return paths, noise, cross-talk... these are all separate concerns. I'll give a summary here.

  • EMC = shielding/designing circuitry to reduce radiated emissions and susceptibility thereof. This is a vast field of study.
  • Return paths = current loops. Things which switch large currents quickly (like digital logic, RF transmitters, motor drivers, switching power supplies, etc.) You have to analyze where these currents flow physically when the switching occurs, and "minimize the loop area." The bigger the current loops (especially >17cm), the more the board could radiate RF unintentionally and interfere with the radio. Smaller loops can also interfere (crosstalk) with other traces, so try to keep power switching away from signal. "Bypass" capacitors (usually 0.1µF ceramic) are placed as close as possible to these switches, which helps to "smooth out" the power spikes generated at that point. GND vias usually help lower resistance and improve EMI/EMC but can hinder return path loops - this really is a whole separate physical layout consideration.
  • Noise - Also a vast field of study. In general, the more rigidly circuit ground is tied to physical ground (chassis and Earth ground), the better. The more % of top (and bottom, for sensitive signals) copper pour are ground, the less noise susceptibility at increasing frequency. Via stitching itself is not a main concern for noise. Routing and loop-avoidance are much more important.
  • And noise can come from the circuit itself, such as by running digital logic traces directly overtop sensitive analog inputs, which is an example of crosstalk. How you route a PCB is increasingly important for faster frequencies, as the higher the frequency, the shorter traces need to be to become antennas.

How would I know if I'd need to use [via stitching] to reduce inductance?

This goes in-line with return paths, noise, and crosstalk. In general, mitigate this by designing the PCB better. This may mean starting over several times with component placement to achieve shortest routes. Keep traces short, use appropriate decoupling caps near switching devices, and use a ground pour on the RF side.

Using a fast oscilloscope, you'd see high-frequency ringing at the peaks and valleys of logic transitions, HF oscillations on power rails, etc. Anything like this might be due to parasitic inductance and capacitance. These form an unintentional L-C tank circuit. Everything conductive has some amount of each. Both can be mitigated by using better components, shorter traces, more space between traces, not looping traces, etc. If a via stitch to ground is a shorter path than a trace, then it will have less of both.

Note, it may be tempting to via-stitch to ground on the pad of a device, such as a decoupling capacitor. This is not advised... it may work for a hand-assembled board, but machine assembly and reflow will tend to "tombstone" or stand these up on their end as the via will suck the solder away from the pad.


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