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I have a CPLD that wants +3.3v and has a maximum allowable current per pin of 8ma. I need to supply a clock signal. The oscillator I selected accepts 5v and outputs 5v-ish levels. I'm finding it challenging to internalize the datasheets of the CPLD and the oscillator.

Now, the oscillator's datasheet says for my clock speed (1MHz), it typically likes 10ma (Supply Current, typical). Which means that as long as 10ma are available at 5v (Supply Voltage, typical) we're gonna have a lot of wiggly fun.

This is where I get confused. Since the output of the oscillator is up to 4.5v (Output Voltage Levels) and this exceeds the 3.3v required by the CPLD, I need to add a resistor. But I don't know what the current should be.

I arbitrarily decided that I will allow 4ma to reach the CPLD. This will prevent the smoke from coming out of it. The oscillator will source 16ma (Output Current) so I believe this isn't a problem. Ohms:

(4.5v-3.3v) = .004R
1.2v = .004a * R
1.2v/.004a = R
300 ohms = R

So a 300 Ohm resistor between the output of the oscillator and the CPLD's clock pin will prevent damage to the CPLD by limiting the current and reduce the voltage to the limits required by the CPLD.

Q1: Does any of this make any sense?

Q2: I assume that when the datasheet says the output current for "1" is -16ma, this means it will source 16ma. Why does the oscillator's datasheet say the oscillator's "0" current is 16ma? I'd have expected 0.

EDIT -

Wow, thanks for the great feedback. I will look for a 3.3v-compatible clock. While in retrospect it's just a better idea, I am surprised that adding a resistor would be so problematic. They seem to be used frequently in digital circuits.

Reference circuit... here's the datasheet for the CPLD. I have not seen a reference circuit as such. However (boy am I dumb!) I do have a working dev board 3' from me that sports an oscillator having "8.000 G MEC AL8GS" stamped onto the tin. (It's my assumption that's the oscillator. Looks like one. The only other thing nearby is a tiny Atmel chip of some sort that I suspect is related to JTAG programming.)

Edit 2 - I'm not married to any particular brand or type of oscillator; for my purposes a low frequency clock is ok. I believe anything over 500KHz would be fine. Back to DigiKey and Mouser!

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  • \$\begingroup\$ NO thats not the way to do it, It might work but if CPLD turns into an SCR from overshoot transients, that's a modest risk way to cause it. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Dec 2 '12 at 13:30
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I highly recommend that you find the reference design for the CPLD and if possible, recreate it and even use the same components. The reason companies provide this is that they want you to get started using their device and unless you have some exotic requirements, it usually does the trick.

You didn't provide the datasheet for the CPLD or the name, but I can tell you that you should choose another oscillator that is 3.3V compatible. CPLDs don't typically operate at 5V and this will likely violate the specs in the datasheet. As I said above, selecting the same as in the reference design (or find any other board that uses the same chip online and see what they're using) will be the best. Trying to reduce the signal level of the oscillator is a very bad idea because you'll introduce all kind of issues such as capacitance, frequencies, noise, etc that are bad bad bad. Even just using resistors will introduce issues that can cause the CPLD to malfunction due to all the capacitance and perhaps loading.

You must make sure that the power supply you have can provide plenty of current for the worst case of the CPLDs. From my experience with FPGAs, the inrush currents are very very large and quick, and you should plan for this. Again, the recommendation is to use whatever a reference design uses and perhaps tweak as necessary.

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CTS now make an identical MX045LV that is spec'd for 3.3V but not listed on D-K site at this time.

Comparing these specs with the MX045 They appear to be identical except configurable to order from 1~108 MHz vs. 1~50 MHz for the LV series. This is normal as lower voltages also reduce the maximum speed of the inverter, but your choice is the minimum so your std 5V Oscillator may operate OK at 3.3V. They don't spec it this way as it affects their universal datasheet from 1~108 MHz and might complicate it to show a declining freq per voltage scale. But I can tell you standard CMOS logic for 74HCUB04 inverter gates most commonly used in such oscillator designs work from 2~6V at 1MHz.

You have 3 choices;

  1. Test OSC from 5V down near 2V for wiggles on output and accept for use at 3.3V ( call factory Tech support to confirm if you must)
  2. Use a resistor divider for the CMOS output using a total of 1~2 mA load to reduce to 3~3.3V range . 5V/1.5mA=3K3 and 3.3/5.0 = 66% so choose 1K1 out and 2K2 to ground. RC time constant for CPLD clock input Ref Chapter 5 p4 specs indicates input is 8 pF. so rise time will be Rs*Cin ~ 5nS so no risk of slowing wiggle edges. and 4.5Vmax Spec actually will result in 3.0V input for Vmax which is fine.
  3. Order the LV part or sample from CTS.
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Your CPLD uses 3.3V logic signals but you chose a 5V oscillator!? That makes no sense. Your basic problem is you picked the wrong oscillator. Get one that runs on 3.3V. Then you can connect its output to the CPLD directly.

As for the current requirements. The datasheet is telling you what the oscillator can drive and still provide a signal within its other specifications. You didn't describe the CPLD, but most likely its clock input is a regular CMOS digital input, which has very high impedance. It won't draw anywhere near what the oscillator can put out. There is no need to try to limit the current into the CPLD input somehow. The CPLD input will only draw a tiny amount in the first place.

Get a 3.3 V oscillator and connect its output directly to the CPLD clock input with no additional parts between, and all will be fine. Don't forget the bypass cap accross the oscillator power and ground pins.

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  • \$\begingroup\$ The current limit desire was obviously an attempt at lazy level shifting. Sometimes tolerable with other signals with careful reading of the specs, but probably not a good idea with a clock. And yes, going to an oscillator with a matching output voltage eliminates the need. \$\endgroup\$ – Chris Stratton Dec 2 '12 at 16:50

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