I am working on characterising a transistor at approximately Vds=1000V and Ids=100A pulsed at around tON=20ns.
Should the power and ground paths (Top and Bottom layers) have vias connected to the respective groundplanes? Will this reduce signal integrity?
From my knowledge, inductance increases when vias are added to the power planes which would compromise signal integrity. However, back-drilling to remove the stubs of the via (e.g. if connected from Top layer to Top groundplane) will improve SI compared to a standard via. Would this give a SI improvement compared to just having a Top layer conductor path?
More specific details can be provided if needed. However, a generalised answer would suffice.