I am working on characterising a transistor at approximately Vds=1000V and Ids=100A pulsed at around tON=20ns.

Should the power and ground paths (Top and Bottom layers) have vias connected to the respective groundplanes? Will this reduce signal integrity?

From my knowledge, inductance increases when vias are added to the power planes which would compromise signal integrity. However, back-drilling to remove the stubs of the via (e.g. if connected from Top layer to Top groundplane) will improve SI compared to a standard via. Would this give a SI improvement compared to just having a Top layer conductor path?

More specific details can be provided if needed. However, a generalised answer would suffice.

  • \$\begingroup\$ given a via has 1nH inductance, the 100 amps switching in 1 naoseb cause 100 volts upset. \$\endgroup\$ – analogsystemsrf Jun 4 '20 at 18:15

Vias have inductance and resistance, if you want to find out how much and if it affects your design, use a calculator tool. In short via inductance is usually measured in nH's and adds a few mΩ's of resistance.

For large currents (10's of Amps) it is probably a good idea to start paralleling vias.

For high frequency signals (50Mhz+) the via inductance will need to be factored into the transmission line to reduce reflections.

  • \$\begingroup\$ I've seen via floods being used for boards of high current. However, I can't understand why it would be a better option if the copper pours are large enough to carry the current. Surely a direct route for current to travel through the copper pour would be more beneficial than adding vias, even in parallel, due to the change in current direction. Unless there's a relationship between the vias and the power plane that is significantly important? \$\endgroup\$ – Azaxa Jun 4 '20 at 18:55
  • \$\begingroup\$ Maybe because if you want to move the trace to another layer, the only way to do so is a via? \$\endgroup\$ – Voltage Spike Jun 4 '20 at 18:57
  • \$\begingroup\$ Sorry, I was unclear. There is no need for my design or the designs I've seen to change layers on the power route. It'll just be a straight connection from the power plug to load resistor to the transistor (with decoupling caps) all on the same layer. \$\endgroup\$ – Azaxa Jun 4 '20 at 19:01
  • \$\begingroup\$ The main reasons to use vias is to 1) change layers 2) wick heat away from copper pours\devices in some instances \$\endgroup\$ – Voltage Spike Jun 4 '20 at 19:03
  • \$\begingroup\$ I understand. So for signal integrity, I'm better off not having any vias as all components are on the top layer. Even though the vias would be connected to a power plane. Thank you for the talk through with this. If this understanding is incorrect please let me know \$\endgroup\$ – Azaxa Jun 4 '20 at 19:08

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