I can't get the Assura system to do simulation of the schematic versus layout. I followed all the steps and inserted all the libraries according to the tutorials and what it is to prescribe writing and I can't simulate someone could give guidance. One of the errors says that the pins are not connected in the layout, but they are connected, yes, has anyone been there?
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1\$\begingroup\$ Please don't shout in your question title. It will get you extra attention but not the sort you want. Hit the edit link ... \$\endgroup\$– TransistorJun 6, 2020 at 22:19
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1\$\begingroup\$ It is not clear what you are trying to do. LVS is the typical step of verifying that a given layout and a given schematic are consistent, that they represent the same circuit. But there is no simulation involved in this. If the tools think you have unconnected pins then you can't extract the netlist from the layout....but you haven't given anywhere near enough information to help. At the very least we need to see your layout and the exact error message. \$\endgroup\$– Elliot AldersonJun 7, 2020 at 0:08
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\$\begingroup\$ Starting Nvn PreExtraction... Starting /tools/cadence/ASSURA41/tools.lnx86/assura/bin/nvn /home/mvictor/pdktsmc180/IRUWB_TRANSMITTER/inverter/inverter.rsf -preExtract -exec1 -cdslib /home/mvictor/pdktsmc180/cds.lib Checking out license for Assura_LVS Checking out license for Phys_Ver_Sys_LVS_XL @(#)$CDS: nvn_64 version av4.1:Production:dfII6.1.8-64b:IC6.1.8-64b.500.9 02/24/2020 20:04 (vmip-172-18-23-226) $sub-version 4.1_USR6_HF7, integ signature 2020-02-24-1834 run on mvictor at Fri Jun 5 21:25:37 2020 \$\endgroup\$– LUFERJun 7, 2020 at 0:58
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\$\begingroup\$ WARNING (AVLVSNN-10029) : 'filter' command has been converted into 'filterOptions' with the same function. 'filter' command is not supported. Use 'filterOptions' instead. Reading schematic network inputting netlist /home/mvictor/pdk/PDK/Assura/lvs_rcx/source.added Reading layout network inputting network ./IRUWB_TRANSMITTER/inverter/inverter.ldb Error: rootCell(or ?cellName) - cell 'inverter layout IRUWB_TRANSMITTER' from the layout does not bind to anything in the schematic. \$\endgroup\$– LUFERJun 7, 2020 at 0:58
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\$\begingroup\$ Finished /tools/cadence/ASSURA41/tools.lnx86/assura/bin/nvn WARNING /tools/cadence/ASSURA41/tools.lnx86/assura/bin/nvn exit with bad status WARNING Status 256 WARNING Assura execution terminated WARNING An error occurred during Nvn PreExtraction. LVS preprocessing requires a successful run of Nvn. Assura will now terminate. WARNING Bad exit from child process .. 0x100 ** aveng terminated abnormally ** ** aveng fork terminated abnormally ** WARNING aveng exit with bad status WARNING Status 256 WARNING Assura execution terminated \$\endgroup\$– LUFERJun 7, 2020 at 0:58
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I think I've already answered your other post, but here it is again:
Problem looks like it's here:
cell 'inverter layout IRUWB_TRANSMITTER' from the layout does not bind to anything in the schematic.
Have you double checked that this layout instance has a corresponding schematic instance in your LVS'd cellview?
They've got to match or the LVS will not complete and throw errors.
