# What happens to copper pours that are 'too narrow'?

What happens to copper pours that are narrower than PCB manufacturer spec?

Let's say spec is 10/10 mils (trace/space) and the copper pour in between soic-08 is only 5mils because it can't be wider (soic-08 pad pitch - 2x 10mil space).

Should I 'take out' that copper pour or leave it there?

Does it get processed? Result?

• There's usually a setting in the layout software, which in effect limits copper pour from going into narrow places. It's called different in different layout software. Which software are you using? – Nick Alexeev Dec 2 '12 at 19:43
• I'm using Eagle 6.2.0 Standard. So basically you are saying that if the copper pour is narrower than the manufacturer minimum trace width, I should prevent copper pour going into those areas? – Tim Dec 2 '12 at 21:01
• +1 "Does it get processed?" I know it's subjective, but I'm interested in the answer. – Garrett Fogerlie Dec 2 '12 at 21:29
• @GarrettFogerlie, somewhere out there there is some shop that will mess this up, but every shop I've worked with will run their own DRC and stop work when they find this issue. – The Photon Dec 2 '12 at 22:29
• @ThePhoton An example for "some shop out there that will mess this up". Sunstone (which is the shop I use and endorse) has various service schedules. The more expensive one PCBExpress has DRC, e-mail notifications, support on the phone. On few occasions, they have identified trouble spots in my boards. Sunstone's cheapest service ValueProto runs light-out, probably. No feedback. But the price is way lower. one and the same shop may or may not mess this up, depending on the pay. – Nick Alexeev Dec 2 '12 at 22:47

It depends on the fab. It's possible that a PCB fab would process these thin areas, but they will be fabed wider than you drew them. Could a that cause a short between the copper pour and a pad? Unfortunately, yes. Removing these risky places to avoid spec abuse is a good idea. Fortunately, this is not difficult to do in the layout software.

In Eagle, change the width property of the copper pour. Below is an example with 2 copper pours. They have identical geometries. The only difference is the width property. The upper pour has width=0.005 (dimensions in inches). The lower pour has width=0.016. Notice that the lower pour didn't "go" between the pads. U1 is SOIC.

• One thing I'd point out is that the lower polygon in your picture has 4 unconnected regions. These regions need to be connected somehow, like with vias to a lower layer, to actually connect them to the required net. – The Photon Dec 2 '12 at 22:27
• Thanks everybody. I got the message: I have to take care that there aren't any copper pours that are thinner than manufacturers minimum trace width. In Eagle "width" parameter for polygon seems to take care of that easy (like Nick explained). Thanks for going through the trouble creating an example. – Tim Dec 2 '12 at 23:23
• It seems you can also remove orphans. – mng Dec 3 '12 at 0:46

What you are doing is violating the design rules for your process, therefore something won't come out right, at least not reliably. Traces may be shorted together if the spacing is too thin, or traces may dissappear if the width is too thin. Some PCB houses will flag the errors and put the board on hold until you tell them what to do. Some may run the board and you get what you get and it's your problem since you violated the rules. Some may automatically delete traces that are to thin.

In any case, it's your fault if they specified the design rules and you gave them specs for something they can't build.

First, most shops in the US prototype business today offer 4/4 design rules as standard. Even if their standard is 6/6, a 4/4 design should result in hardly any premium charge. So if your design ended up with a 5 mil copper feature, you should be able to get this manufactured with no problems, so long as you choose the right shop and specify the correct rules.

But, lets imagine you are designing for extremely high volume and want to get the absolute best price, so you are designing for 6/6 or even 8/8 rules. In that case, the best thing to do is make your design tool aware of your rules. I can't help with Eagle specifically, but any worthwhile layout tool should have settings for the space/trace design rules, and it should respect them when laying out polygons.

Even if your tool doesn't do this, there should be workarounds. The key thing is that polygons are built by simply serpentining a long trace back and forth to fill an area. As Nick shows, one work around is to change the width of this long trace so that it won't fit into the gaps that are causing the problem. The trade-off, as you can see in Nick's images, is that other features of the polygon, like the corners, becomes more coarse or rounded.

Another option is that most layout tools have fairly sophisticated design rule options (unfortunately if your tool is so simple that it can't understand a simple space/trace design rule, this might not be available to you). For example, you should be able to specify a specific clearance rule for polygons on the top layer and SOIC footprints. If you increase this clearance, you should be able to prevent the tool from attempting to fill the space between the pads.