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I am reading this application note from Texas instrument : http://www.ti.com/lit/an/slyt187/slyt187.pdf?ts=1591543592096&ref_url=https://www.google.fr/. The application note give us the transfer function Vout/Iout of an LDO built with a PMOS. Here is the model :

enter image description here

Here is the transfer function :

enter image description here

where R12 is equal to :

enter image description here

I have actually some troubles to understand why Rds is in parallel with the capacitor Cb. The voltage across Rds is equal to (Vin - Vout) and the voltage across Cb is equal to Vout ? So why Rds is in parallel with Cb ?

Thank you very much and have a nice day :D (I know that I have some troubles with AC model)

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    \$\begingroup\$ That's not the transfer function, that's the output impedance. \$\endgroup\$
    – Marcus Müller
    Commented Jun 7, 2020 at 18:56
  • \$\begingroup\$ Vout/Iout cannot be a transfer function ? \$\endgroup\$
    – Jess
    Commented Jun 7, 2020 at 19:03
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    \$\begingroup\$ sure, that's the transfer of the output impedance without load. Not the transfer function of the complete system. \$\endgroup\$
    – Marcus Müller
    Commented Jun 7, 2020 at 19:32
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    \$\begingroup\$ It's a good article but has (minor) errors in schematic. Vi is assumed AC short (ideal) yet R1,R2 >> Rds so R1, R2 can be neglected. Zo "shud be" left of load. \$\endgroup\$
    – D.A.S.
    Commented Jun 7, 2020 at 19:48
  • \$\begingroup\$ Thank you for your comments. Do you know where I can find a better model than this one ? I found also this one but it is clearly a complex model, nevertheless it might be the right one ! onsemi.com/pub/Collateral/AND8037-D.PDF \$\endgroup\$
    – Jess
    Commented Jun 8, 2020 at 15:01

1 Answer 1

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I have actually some troubles to understand why Rds is in parallel with the capacitor Cb.

When we're working out the equivalent resistance of some network, we treat ideal voltage sources as shorts. In this analysis we're assuming the input (\$V_i\$) is being provided by an ideal voltage source. Therefore the source terminal of the PMOS is connected to ground, for the purpose of this analysis.

Since \$C_b\$ is also connected between the output terminal and ground, that puts \$C_b\$ and the drain-source branch of the MOSFET in parallel.

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