# MOSFET drain current equation vs on resistance

I have a very simple circuit. It’s just an n-channel enhancement MOSFET where Vgs is being driven to 9V and a relatively small 9ohm resistor sits between the 9V battery and drain terminal.

The way I went about the analysis was to assume the MOSFET is saturated and then use: Id = Kn(Vgs-Vt)^2 where Kn is the transconductance parameter (W/LμC_ox) and Vt is the threshold voltage. For a Kn in the order of 1mA/V^2 and Vt approximately 1V, we get a drain current in the order of 8mA. These are all relatively standard values (I think).

When I simulate the circuit on LTSpice the current is in the order of 1A and it appears the simulation just treats the MOSFET as having a low on resistance between drain and source terminals so that the drain current is essentially just 9V/9ohm.

These two answers are two orders of magnitude apart, so it cannot be the case that the parameters I used in the simulation/calculation were just off (I simulated with a bunch of MOSFETs on LTSpice). To me it seems like there is something more fundamental that I’m not understanding in my calculations. When is it correct to use that above drain current equation and when should I rather treat the MOSFET as just being a small resistor between drain and source terminals (when turned on)? I’m assuming the drain current equation isn’t used that often because I can’t really find a value for Kn in datasheets. • Why do you assume that you have an appropriate transconductance parameter? When you simulated in LTspice, exactly what NMOS model did you use? How was the body connected? Jun 7 '20 at 21:33
• Idsat = Kn/2*(Vgs-Vtn)^2. Jun 7 '20 at 21:37
• I studied the MOSFET chapter out of Microelectronics by D. Neaman. There the transconductance parameter was mentioned as being in the order of 200u - 2m. I used a few different models in LTSpice (just randomly selected a bunch) including IRFH5302, A06408, BSC032N, and about 5 more. But they all gave me similar answers Jun 7 '20 at 21:42
• Since Vgs> 3Vt, It is ~ fixed minimal RdsOn in linear mode Normally I use Vgs>=2.5x Vt for linear mode Jun 7 '20 at 22:02

The $$\R_{ds}(on)\$$ spec doesn't apply to saturation mode.

It applies in the linear or triode operating mode, where the current through the channel depends strongly on both $$\V_{gs}\$$ and $$\V_{ds}\$$. That does mean that $$\R_{ds}(on)\$$ is not really a fixed number but depends pretty strongly on $$\V_{gs}\$$, and the $$\V_{gs}\$$ where the specification is measured should be stated clearly in the datasheet.

For example, in the Vishay IRF530 datasheet: Why do you assume you are in saturation?

Here are the saturation conditions:

1) Vgs > Vth. True.

2) Vds > Vgs - Vth. False.

At this DC bias, Vds is approximately 0. Vgs is approximately 9V.

0 > 9-(volt or two for Vth) is False.

• assuming SAT, Idsat formula gives 32 mA of current using the Kn and Vtn provided by OP. 9 - 9*0.032 is around 8.7 V which is Vdrain and also Vds. So, Vds is indeed higher than Vgs - Vtn and SAT assumption validated. Jun 7 '20 at 22:15
• Models have limits. You assume SAT (which is wrong) and then attempt to apply the saturation equations (which then give nonsensical answers) and then use that to justify that you are in SAT. If you look at Fig. 1 in the IRF530 datasheet, you see that 9V Vgs and 8.7 Vds and 32mA cannot exist simultaneously (Vgd is < Vth). Basically, 32mA and Vgd = 0.3V is insufficient current to form the channel required for saturation at the drain terminal. A more complete discussion of saturation is at the bottom of here: ecee.colorado.edu/~bart/book/book/chapter7/ch7_3.htm Jun 9 '20 at 0:29
• This does not justify you. "At this DC bias, Vds is approximately 0. Vgs is approximately 9V." without any background, you both use formulas of the model and blame the model. Sorry, but not a good answer. Jun 9 '20 at 2:03