I'm very new to hardware logic (and this site) but I'm trying to understand the exact use and duration of the asynchronous inputs clear (CLR) and preset (PRE) on flip-flop timing diagrams. They seem to typically both be active-low triggered. I know that CLR sends the Q outputs to 0, while PRE sends them to 1, both regardless of what edge the clock is on (if any). What I'm not sure about, is the duration after the initial clear or preset. In other words, does Q just go to 0 on clear but only when clear is first low, then can be dependent on the inputs (JK, T, D, SR) again? Or does Q stay low for the entire duration of time that CLR is low? Similarly for PRE, would PRE send Q outputs high for the entire time that PRE is high, or is it only initially when PRE first goes high? Thanks for your patience as I'm learning.
As you mention, asyncronous SET and RESET signals are often active low. To simplify the explanation, let's assume we're doing a RESET. (PRESET will work the same way.)
The Q output will be driven LOW as soon as the RESET is pulled low.
The Q output will remain LOW as long as the RESET is held low, regardless of other signals.
At the trailing (rising) edge of the RESET pulse, the Q output will remain LOW until the next clock, when it will reflect the state of the flip-flop.
The TTL active low terms Preset and Clear (Pre,Clr) pre-date the identical terms Set and Reset (S,R) which are more common in CMOS and often "active high".
If both inputs are active is the only time when Q and Q_ are both high i.e. not complementary. ("active" meaning for above inputs in active state)
Set has priority over Q and Reset has priority over Q_ (read Q bar).
When the above is true, The 1st to go inactive determines when it's corresponding primary output toggles. (i.e. if S and R are both active and R is removed 1st while S is still active, then Q_ toggles from high to low to satisfy Set as still active.
Both being latched inputs, they can be removed as soon it enters the active state and may be removed immediately which is used in hand-shaking communication logic or to preset aynchronous counters quickly.
The smallest pulse may be generated by gating the either output(Q,Q_) and externally gated with the either input(S,R) so that the input condition is removed immediately after the output goes active. (respectively) This is how Flip flops are used in edge-sensitive asynchronous phase detectors a.k.a Type II mixers in PLLs.
An example below of the guaranteed narrowest pulse one-shot generated using a FF and external gate to turn off the ClR input as soon as the output changes due to D being 1 and clocked in.