State Space Average Model of Non-Ideal Buck Converter

Question

I've been learning power electronics and am trying to design a dual-switch forward converter. One of the things I've been trying to do is derive the small-signal equivalent circuit of the non-ideal forward converter. The part I'm having difficulty with is how to write the state equations when the ESR of the capacitor is included.

In order to better understand the model of the forward converter I'm following along with a state-space-averaging example of a non-ideal buck converter. This Paper describes on page 8 how perform a state space averaging on a non-ideal buck converter, which is similar to the forward converter since the forward converter is a buck-derived topology and the equations are nearly identical. The circuit is:

We can define the state vector containing the inductor currents and capacitor variables x(t), input vector u(t) and output vector y(t) as:

Where Vg(t) is the input voltage, Ig(t) is the input current and v(t) is the output voltage.

Now, we need to write the state equations for the circuit during the first sub-interval when the transistor is on. During this interval the transistor is replaced by an equivalent resistance Rt and the free-wheeling diode is an open-circuit. The state equation of this linear circuit are of the form:

With the following matrices:

In expanded form this translates to:
\

Which are the equations for the first interval. Where R1 is the inductor parasitic resistance, R2 is the capacitor ESR, Rt is the on resistance of the transistor and R is the load resistance. I'm confused about the how the author derived these state equations. I'm sure there's something simple I'm missing in the circuit analysis, but I'm not able to get the KVL and KCL equations for my inductor voltage and capacitor current to match in order to get the SSA model of the converter in equillibirum. If someone could walk me through there derivation or provide hints I would greatly appreciate it. I've done SSA on various other converters and understand the process well, but the added complexity that the ESR's introduce is giving me difficulty. Thank you.

Answer 1

If you examine all the parasitics of an IC_implemented regulator, including Feedback Node and Power Device drain/substrate capacitance, etc etc, you have about 12 order system.

How do you chose which of those to ignore?

I recall a guy hired to implement battery charger designs on silicon.

He had a PhD in switching regulators.

Two years after hiring, he still could not avoid "chaotic" behaviors in the circuits, ON THE BENCH.

Which of the 12 L or C elements are you ignoring? Do you care? Should you

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The reason I mention these (numerous) parasitics is the need for quality mindset in design.

To produce a product that becomes very respected, known as trouble_free, and works well in many situations, despite silicon_process variations, seems to require AWARENESS of the design margins.

And design margins are not easily verified ON THE BENCH.

Design margins are a task for your brain, and possibly for a simulator.

For your reading delight, examine almost any issue of IEEE "yellow rag" Journal on Circuits and Systems in the 2000 --- 2005 era. Switcher stability was discussed in just about each of the 12 issues each year.