# State-space average model of non-ideal buck converter

I've been learning power electronics and am trying to design a dual-switch forward converter. One of the things I've been trying to do is derive the small-signal equivalent circuit of the non-ideal forward converter.

The part I'm having difficulty with is how to write the state equations when the ESR of the capacitor is included.

In order to understand the model of the forward converter better I'm following along with a state-space-averaging example of a non-ideal buck converter. This Paper describes on page 8 how to perform a state-space averaging on a non-ideal buck converter, which is similar to the forward converter since the forward converter is a buck-derived topology and the equations are nearly identical. The circuit is:

We can define the state vector containing the inductor currents and capacitor variables x(t), input vector u(t) and output vector y(t) as:

Where Vg(t) is the input voltage, Ig(t) is the input current and v(t) is the output voltage.

Now, we need to write the state equations for the circuit during the first sub-interval when the transistor is on. During this interval the transistor is replaced by an equivalent resistance Rt and the free-wheeling diode is an open circuit. The state equations of this linear circuit are of the form:

With the following matrices:

In expanded form this translates to:

Which are the equations for the first interval. Where R1 is the inductor's parasitic resistance, R2 is the capacitor's ESR, Rt is the on-resistance of the transistor, and R is the load resistance.

I'm confused about the how the author derived these state equations. I'm sure there's something simple I'm missing in the circuit analysis, but I'm not able to get the KVL and KCL equations for my inductor voltage and capacitor current to match in order to get the SSA model of the converter in equilibrium.

If someone could walk me through there derivation or provide hints I would greatly appreciate it. I've done SSA on various other converters and understand the process well, but the added complexity that the ESRs introduce is giving me difficulty.

• I would not recommend state-space averaging (SSA) for studying the basic switching cells such as buck, boost and buck-boost. Instead, the PWM switch model is a simpler and more intuitive way for looking at the small-signal response of a switching converter. Have a look at the APEC seminar I taught in 2013 which covers the subject extensively. One really cool advantage of the PWM switch over SSA is its invariance: the internal equations of the model remain the same regardless of the adopted topology. Jun 9, 2020 at 6:33
• Thank you for the reply! Interestingly enough, I actually own two of your books (which I've learned a lot from, so thank you) so I will definitely avail myself of the info on average switch modeling! I was originally dissuaded from trying to use the PWM switch model for the dual-switch forward converter because of the number of switching elements, but maybe it's not as complicated as I imagine? Jun 9, 2020 at 19:56
• The complexity with the SSA is that not only you have to linearize the newly-obtained time-continuous equations but then you need to come up with an equivalent electrical circuit from which you work out a transfer function. And if you realize that you want to see the effect of an extra resistance you forgot, then you restart from scratch! The 2-SW forward is simply modeled as a 1-SW forward which is an isolated buck converter: $V_{in}$ is replaced by $NV_{in}$. A simple analysis with the PWM switch. Honestly, try it and you won't touch SSA anymore at least for common switching cells. Jun 9, 2020 at 20:31
• Thanks for the info. Out of curiosity, why can you model the 2-SW forward converter as a 1-SW forward converter? Jun 12, 2020 at 23:50
• Output inductor current and capacitor voltage remain similar whether you use a 2-SW or 1-SW approach: you still drive the $LC$ network with a low-impedance square wave whose amplitude is $NV_{in}$. Jun 13, 2020 at 7:40

## 2 Answers

i myself struggled with this too. I will show how to derive the equation for a system only containing the ESR resistor for the Inductor and capacitor, as these are the parts bringing some complications.

Using KCL, we can derive that: $$I_L = I_1 + I_2$$ using ohms law, this can be rewritten as: $$I_L = \frac{V_o-V_c}{R_c} + \frac{V_o}{R_L}$$ From here we simply solve for Vo: $$I_L = \frac{V_o-V_c}{R_c} + \frac{V_o}{R_L}$$ $$I_L = V_o * ( \frac{1}{R_c}+\frac{1}{R_L}) - \frac{V_c}{R_c}$$ $$I_L+\frac{V_c}{R_c} = V_o * ( \frac{1}{R_c}+\frac{1}{R_L})$$ $$\frac{I_L+\dfrac{V_c}{R_c}}{\dfrac{1}{R_c}+\dfrac{1}{R_L}} = Vo$$

Now we will look at the output voltage using KVL.The following can be shown: $$V_g - V_L - I_L*R_s = V_o$$ We also know that VL is given as a differential equation: $$V_L = \frac{di_L}{dt}L$$ Thus we can say that: $$V_o = V_g - \frac{di_L}{dt}L - I_L*R_s$$

This can then be placed instead of Vo in the equation found using KCL: $$\frac{I_L+\dfrac{V_c}{R_c}}{\dfrac{1}{R_c}+\dfrac{1}{R_L}} = V_g - \frac{di_L}{dt}L - I_L*R_s$$

$$-V_g + I_L*R_s+\frac{I_L+\dfrac{V_c}{R_c}}{\dfrac{1}{R_c}+\dfrac{1}{R_L}} = - \frac{di_L}{dt}L$$

$$V_g -I_L*R_s -\frac{I_L+\dfrac{V_c}{R_c}}{\dfrac{1}{R_c}+\dfrac{1}{R_L}} = \frac{di_L}{dt}L$$ $$V_g-I_L*R_s - \frac{I_L}{\dfrac{1}{R_c}+\dfrac{1}{R_L}} - \frac{V_c\dfrac{1}{R_c}}{\dfrac{1}{R_c}+\dfrac{1}{R_L}} = \frac{di_L}{dt}L$$ $$V_g -I_L*R_s- I_L\frac{1}{\dfrac{1}{R_c}+\dfrac{1}{R_l}} - V_c\frac{R_L}{R_c+R_L} = \frac{di_L}{dt}L$$ $$V_g -I_L*R_s- I_L(R_c || R_L) - V_c\frac{R_L}{R_c+R_L} = \frac{di_L}{dt}L$$

$$V_g +I_L(-R_s-(R_c || R_L)) - V_c\frac{R_L}{R_c+R_L} = \frac{di_L}{dt}L$$

And from here one can directly insert the values in a matrix. I hope this helps

If you examine all the parasitics of an IC_implemented regulator, including Feedback Node and Power Device drain/substrate capacitance, etc etc, you have about 12 order system.

How do you chose which of those to ignore?

I recall a guy hired to implement battery charger designs on silicon.

He had a PhD in switching regulators.

Two years after hiring, he still could not avoid "chaotic" behaviors in the circuits, ON THE BENCH.

Which of the 12 L or C elements are you ignoring? Do you care? Should you

=============================

The reason I mention these (numerous) parasitics is the need for quality mindset in design.

To produce a product that becomes very respected, known as trouble_free, and works well in many situations, despite silicon_process variations, seems to require AWARENESS of the design margins.

And design margins are not easily verified ON THE BENCH.

Design margins are a task for your brain, and possibly for a simulator.

For your reading delight, examine almost any issue of IEEE "yellow rag" Journal on Circuits and Systems in the 2000 --- 2005 era. Switcher stability was discussed in just about each of the 12 issues each year.

• This is for educational purposes so it's definitely not an exhaustive study, just meant to enhance my understanding of the dynamics of smps. Also, it's my understanding that higher order polynomial transfer functions such as those found in converter systems can be approximated/simplified with algebraic methods (if later verified on the bench), but I'm very new to the subject. Regardless, a 12 order system sounds truly horrific! It is a good point that you're making about which of the parasitics i'm ignoring. For now, the reason i'm ignoring them is just for simplicity :) Jun 9, 2020 at 2:55