Good day all. I am trying to process two signals to produce an output signal. I will be posting a picture for clarity (sorry if I used pencil, I am stucked at home). My two input signals are sig, a 20 Hz and 50% duty cycle signal and EN, a signal that is manually controlled by user via switch. The time duration Thigh of EN (active-high) is expected to be much larger than the period of sig (50ms). What I want to do is make a digital circuit to create an output signal, EN'. EN' is created by delaying all edges of EN (+ and - edges) until the next rising edge of sig. I have read a little about flip flops, which appears to be an answer for circuits which require time delay. Can anyone point me or suggest me some starting point for type of IC/flip flop that I might use?

I am currently considering T flip flop. When I look at what I want to happen (see picture), I see that I need delaying and toggling. I want to somewhat modify T flip flop such that instead of toggling Q when T = 1, the circuit would instead toggle Q only one time during every Thigh of sig OR toggle Q only during rising edges. enter image description here

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    \$\begingroup\$ What you really want is a D flip-flop, which simply copies its input to its output on every rising clock edge. BTW, your diagram shows something else. \$\endgroup\$
    – Dave Tweed
    Jun 9 '20 at 1:13
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    \$\begingroup\$ In Verilog: always @(posedge sig) EN_prime <= EN; \$\endgroup\$
    – Dave Tweed
    Jun 9 '20 at 1:24

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