I have a verilog combinational circuit and I have written a testbench which uses a test vector containing 32,768 testcaes. At the moment I am performing exhaustive testing. How can I reduce the number of testcases while ensuring the circuit is properly tested.
This depends a great deal on what your circuit does, and what kind of a test you are trying to create.
If what you really want to do is verify that the design is correct then you need to think about what the design is really supposed to do. Look for "don't care" conditions in the specifications for the circuit, and avoid running tests for all of the "don't care" cases.
If you are instead trying to create a manufacturing test, to verify that a device was manufactured as designed, then you need to think about fault coverage. That is, if a particular fault occurs in my circuit will I be able to observe a difference in the outputs? A fault is usually modeled as some node in the circuit that is "stuck" at logic 1 or logic 0. This is a broad area of research and design work, and you would probably want to use a fault simulator to give you quick answers. If your circuit is small enough there are manual ways to devise a minimal set of test vectors.