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I am working on a PCB layout on a very space constrained, 4-layer board. On the board is a MIPI-output image sensor (1 lane) which go to an FPGA.

  • Layer 1: Image sensor
  • Layer 2: Full Gnd plane
  • Layer 3: Some signals, some 1.2v plane
  • Layer 4: FPGA

Since the board is very small, the differential pairs are only about 10mm (40 mils) long. At this length, do I still need to be very careful about their layout?

Here's what I have now:

MIPI FPGA

The FPGA is at the top of the image, on the blue (bottom) layer. The Image sensor is at the bottom of the image, shown in grey (top layer).

And here we can see Layer 3 under the differential pairs.

MIPI FPGA reference plane

As you can see, this plane doesn't fully cover the differential pairs. And when the pairs change layers, and thus change reference planes, the nearest capacitor, to help move the return current between planes, isn't that close (red circles).

One last point, there is clearly a change in impedance as the tracks change from 0.075mm (3 mils) to 0.12mm (5 mils).

The question is, does all of this matter when the pairs are so short?

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  • \$\begingroup\$ Are you using blind/buried via's? Are the via's that the diff pair crosses in the first picture blind? \$\endgroup\$ – Ron Beyer Jun 9 '20 at 20:19
  • \$\begingroup\$ If it is a very small board, consider going 6 layers and having proper reference planes for the diff pairs. The cost delta might not be that big. \$\endgroup\$ – Lior Bilia Jun 9 '20 at 20:19
  • \$\begingroup\$ @RonBeyer - Sorry, I forgot to mention that the big vias are through, while the small vias are blind, joining layers 3 and 4. \$\endgroup\$ – Rocketmagnet Jun 9 '20 at 21:00
  • \$\begingroup\$ @LiorBilia - That's a possibility. What I'd really like to know is whether this design is likely to work, or likely to fail. \$\endgroup\$ – Rocketmagnet Jun 10 '20 at 9:54

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