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I want to be able to output correct data from the microcontroller to the 74HC595 shift register without using the clock lines separately. This schematic matches my ideas for 16 bits of data:

Shift register

The micro I'm using is 8051 based (at89C2051).

If the RCK and SCK lines were connected to the microcontroller separately, then my code to send out the data would be as follows:

RCK equ P1.1
SCK equ P1.2
DATA equ P1.3
LOWBYTE equ 20h
HIGHBYTE equ 21h

clr SCK
clr RCK
mov A,HIGHBYTE
mov R1,#8h
send1:
  rlc A
  mov DATA,C
  nop
  setb SCK
  nop
  clr SCK
djnz R1,send1

mov A,LOWBYTE
mov R1,#8h
send2:
  rlc A
  mov DATA,C
  nop
  setb SCK
  nop
  clr SCK
djnz R1,send2
setb RCK
nop
clr RCK

But I don't have enough GPIO pins on my micro to allow for separate clock lines and I don't have enough board space for a larger micro. So I attempted code with the lines tied together as follows. Here, CK means all clocks tied together:

CK equ P1.2
DATA equ P1.3
LOWBYTE equ 20h
HIGHBYTE equ 21h

clr CK
mov A,HIGHBYTE
mov R1,#8h
send1:
  rlc A
  mov DATA,C
  nop
  setb CK
  nop
  clr CK
djnz R1,send1

mov A,LOWBYTE
mov R1,#8h
send2:
  rlc A
  mov DATA,C
  nop
  setb CK
  nop
  clr CK
djnz R1,send2

Somewhere, someone mentioned that the shift clock (SCK) is one ahead of the data latch clock (RCK) when they are tied and used together, but how do I apply this into my code and still ensure the correct 16-bits are sent on the shift register output lines?

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  • \$\begingroup\$ Hint: You could possibly use a inverter on the clock line so a rising edge shifts data while the falling edge loads the register, but you may want the order to be opposite of what I wrote. In such a case just reverse the rise/fall connections. \$\endgroup\$ – user105652 Jun 10 '20 at 0:08
  • \$\begingroup\$ Note that with the scheme I mentioned you are NOT loading a byte at a time, but a single bit at a time. Try to come up with a spare pin for crucial hardware control. \$\endgroup\$ – user105652 Jun 10 '20 at 0:10
  • \$\begingroup\$ So you're saying I'm better off to never join the clocks together in the first place? (time for more complex wiring I guess....) \$\endgroup\$ – Mike -- No longer here Jun 10 '20 at 1:42
  • \$\begingroup\$ Mike, you really do NOT want to tie SRCLK and RCLK together. Or, if you do tie them together you do need to be aware that the gating system won't work as expected. (In fact, I'm not sure the behavior is specified in that case.) If you wire up an inverter between SRCLK and RCLK, that will work fine, though. Keep SRCLK hooked directly to your MCU. Use an inverter between that line and RCLK. Otherwise, it's really nice to have RCLK, separately. That allows you to shift stuff in without affecting the output until you are ready to latch it out. (Or you can use the /OE line, I suppose.) \$\endgroup\$ – jonk Jun 10 '20 at 2:03
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Ideally you want to load in 16 bits of data using the SCK, then output all 16 bits in parallel using the RCK. Binding SCK and RCK together makes normal shift / load operation neigh impossible. Normally OE/G is low so outputs are always ON. No need to turn off unless another 74LS585 pair would be driving the same 16 outputs

If all 16 outputs need to maintain state and then change state at the same time then a proper shift / load sequence must be done.

The idea of using an MPU properly is to reserve as many pins as required to get control of external hardware. This requires detailed planning up front so you assign mandatory functions first.

Excessive pins are much better than coming up short on mandatory control pins.

Just out of curiosity, how did you come up short a control pin on a 20 pin MPU? Were the rest of the pins already committed to existing hardware?

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