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I'm wondering what type of buffers/techniques are typically used for connecting a cpu register(flip flops?) to a cpu bus(data/address/control). Since there are many registers on a single bus, I know there has to be some kind of tristate mechanism but how do you specify which buffers should be floating?

Thinking logically, there should be some kind of register select bit along with a read/write bit that toggles which register is in use and what it is doing with the value. Even though this makes sense to me, I don't think it is practical to AND every register input with a register select or r/w bit.

I've been searching the internet for schematics or documentation and I can't find any solid information. Most cpu schematics are so complicated that I'm having a hard time making sense of them. Any help is greatly appreciated.

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In some device technologies, registers are connected to a bus using three-state outputs. Such an approach does have some advantages, but it generally either requires that either there be some "dead time" between the moment one register releases the bus and the moment another register starts driving it, or else runs the risk that a device might start driving the bus before the previous device has fully released it.

In other technologies, this approach is avoided in favor of using nested multiplexers. If there are 64 registers that can output to a bus bit, the device might have eight 8-way multiplexers each of which accepts input from one register, and one more 8-way multiplexer which accepts input from one of the first eight. While this may use slightly more circuitry than the bus-based approach, it has the advantage that every signal throughout the system will be driven by exactly one device at all times.

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  • \$\begingroup\$ Good answer; however, I'm looking more for specifics on how a 'three state ouput' would work. Do they only clock the registers that need to use the value on the databus(so the others don't change)? What type of chips between the bus/register are used? Your second paragraph has some great information, thanks! \$\endgroup\$ – Dave C Dec 3 '12 at 20:01
  • \$\begingroup\$ @DaveC - Try looking at the schematics/designs of the custom/home built TTL computers out there, there's lots of nice info there. \$\endgroup\$ – Trygve Laugstøl Dec 29 '12 at 0:35
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    \$\begingroup\$ @DaveC: The expected design would be that every register ignores the bus except when it needs to either put its contents there or load its contents from there. Depending upon the design topology, the bus may be floating, weakly pulled high or low, weakly held in its current state (whatever that happens to be), or actively pulled high or low when nothing else is driving it. In general, CMOS gates draw extra current when their inputs are near mid-rail (and a bus which isn't driven at all could float to a near-mid-rail voltage), but... \$\endgroup\$ – supercat Dec 31 '12 at 19:28
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    \$\begingroup\$ ...it's not difficult to design a CMOS NAND gate in such a way that if one input is low, it won't matter if the other input is mid-rail; likewise one can design a NOR gate so that if one input is high, the other won't matter. \$\endgroup\$ – supercat Dec 31 '12 at 19:29
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Have you considered perhaps looking at the datasheet of a part once used to implement registers in a CPU, such as the 74HC574 datasheet?

It works exactly as you suspected:

One register select bit (a pin named CLK) for WRITE that, on its rising edge, tells the chip to take the data on its input pins and store it internally. A CPU that included lots of these chips would only clock the register(s) that need to store the value currently on the databus, and not clock the other registers that need to hold their internal values.

Another register select bit (a pin sometimes called "nOE") for READ that, as long as it is low, tells the chip to drive its internal data out on the data bus.

Register files inside a FPGA are conceptually the same.

how do you specify which buffers should be floating?

Typically somewhere else in the CPU is the instruction register (IR). Typically a decoder something like the 74HC138 decodes the "source field" from the instruction register into a bunch of nOE lines, one for each register. The 74HC138 makes sure that at most one register drives the databus at any one time, so there's no conflict. The 74HC138 holds the nOE of all the other registers high, so their output pins are effectively "disconnected" ("tristated", "disabled", etc.). I wouldn't say their output pins are "floating" though -- each pin connected to some particular bit of the databus is being driven high or low by the one chip that is selected by the 74HC138.

A similar demultiplexer decodes the "destination field" from the instruction register into a bunch of CLK lines, one for each register, and the CPU designer adds a little extra circuitry to pulse the clock at exactly the right instant, a little after the data has stabilized on the bus, and a little before some other source register has selected and the data begins changing again.

every signal throughout the system will be driven by exactly one device at all times.

That could work. However, in practice, I've never seen a register file -- on a monolithic IC, or built out of TTL chips, or built out of even simpler components -- built entirely out of cascading muxes. The ones I've seen always include at least one bidirectional 3-state bus somewhere.

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  • \$\begingroup\$ Many types of programmable logic have no concept of an internal bus with multiple 3-state drivers. Register files built out of such logic (as opposed to the purpose-built register-file circuitry which is often included in FPGA chips) are thus typically mux-based. Note also that the output of a synchronous mux-based register file need not have any "dead interval" between the time one register stops outputting its data and the time the next one starts. Using 3-state logic often requires either a willingness to accept either dead time or intermittent bus contention. \$\endgroup\$ – supercat May 30 '13 at 18:06
  • \$\begingroup\$ If a register file is implemented as a regular structure within a monolithic IC, it may be (often is) possible to control the enable-line timings sufficiently well to minimize the necessary dead interval. Further, in many situations, requiring the bus to be idle between reads of different data may not pose a problem. Nonetheless, 3-state approach requires an attention to certain aspects of timing which would not be an issue with a mux-based approach. \$\endgroup\$ – supercat May 30 '13 at 18:12
  • \$\begingroup\$ @supercat: I would like to mention such mux-based register files in a book I'm helping to write. Do you have links to any good examples? (Should I ask this as an independent question?) \$\endgroup\$ – davidcary May 31 '13 at 17:59

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