# Difference between 'high in vhdl and $high in verilog Is there any difference between 'high in vhdl and$high in verilog??

• Generally speaking, yes - both return the highest index possible. But maybe a more specific question would yield a more specific answer. Jun 11, 2020 at 11:47

The difference is \$high in Verilog can only return a integer type whereas the 'high attribute in VHDL returns the largest value in the type of the range.