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I intend to use a buffer with three-state output in one of my designs. The datasheet of the buffer IC shows the following circuit:

circuit for buffer with three-state output

What's the purpose of CL, RD and RU on the output of the buffer. As I understand the values of RU and RD are equal - leaving the output floating between VI and GND maybe? But why?

Link to the datasheet: NC7SZ125

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  • \$\begingroup\$ Which buffer? Please link to buffer datasheet or at least tell the make and model. \$\endgroup\$
    – Justme
    Jun 11, 2020 at 15:10
  • \$\begingroup\$ That is a test circuit and the switching waveforms in the datasheet will have been characterised using this circuit as well as (possibly) short circuit current. \$\endgroup\$ Jun 11, 2020 at 15:15
  • \$\begingroup\$ @Justme I updated the question and added a link to the NC7SZ125 datasheet. \$\endgroup\$ Jun 11, 2020 at 15:19
  • \$\begingroup\$ @PeterSmith yes, you may be right, thank you! So, this wouldn't be relevant in an application setting then? \$\endgroup\$ Jun 11, 2020 at 15:20

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The datasheet is showing you the test circuit they used to test the buffer.

The propagation delay are specified into a certain CL.

The output enable and disable times are specified with a certain CL, RU and RD.

If your circuit stray capacitance and load capacitance are less than CL, then you should get at least the specified performance from the buffer.

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  • \$\begingroup\$ This actually makes a lot of sense, thank you! So, no additional circuitry needed to use the buffer then? Except maybe some decoupling, of course. \$\endgroup\$ Jun 11, 2020 at 15:24
  • \$\begingroup\$ Certainly some power supply decoupling. If you do need fast enable or disable, then you need to think about what other loads are sharing the output line, whether it's static pullups/downs, or other buffers that also get disbaled/enabled. \$\endgroup\$
    – Neil_UK
    Jun 11, 2020 at 15:28

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