Does dividing a clock increase its jitter?

Question

I want to have my microcontroller and ADC using a clock derived from the same source in an effort to avoid intermodulation effects. All clocks are under 50 MHz.

The maximum SNR out of an ADC is bounded by the jitter of its sampling clock. This means that I want to make sure to keep the jitter of the sampling clock below some threshold.

Does anyone have some information on a good way to handle this, or some information about gotchas? I looked at some of the fancy clock/divider ICs, but they are overkill in price, power, and frequency.

So far I've thought about two methods.

1. Use external ICs like flipflops to divide down the clock.
2. Use the timers/counters in the MCU to divide down the clock and output it to the ADC.

I tried to find some information about how much a clock will degrade when passed through flipflops or MCU timers/counters, but I couldn't find any information.

Answer 1

As long as the divider is using only one edge of the input clock, and only one edge of the output clock is being used by the ADC, then no, there will be no significant increase in jitter.

The output edges will have the same peak-to-peak jitter as the input edges, in terms of absolute time (ps or ns). But expressed as a fraction of the output clock period (% UI), the jitter will be reduced by the division ratio.