I plan to use IC AK4430, an I2S digital interface sound output chip, to be connecte to an ESP-07 Wifi module via 3 wires (BITclk, LRclk and DATA). But the IC also require an input signal that they call as MCLK (master clock).
AK4430 HTML datasheet: https://www.digikey.com/htmldatasheets/production/755129/0/0/1/ak4430.html
Page 9 of datasheet shows this:
The external clocks required to operate the AK4430 are MCLK, LRCK, and BICK. The master clock (MCLK) should be synchronized with LRCK, but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the delta-sigma modulator. Sampling speed and MCLK frequency are detected automatically, and then the internal master clock is set to the appropriate frequency (Table 1). The AK4430 is automatically placed in power saving mode when MCLK, LRCK and BICK stop during normal operation mode, and the analog output goes to 0V(typ). When MCLK, LRCK and BICK are input again, the AK4430 is powered up. After exiting reset following power-up, the AK4430 is not fully operational until MCLK, LRCK and BICK are input.
And also shows the following table also at page 9:
From the table, if I pick freqSampling/fs = 44.1 Khz and MCLK = 512*fs, then MCLK would be 22.5792 Mhz.
That 22.5792Mhz SMD 4-pin oscillator could be used: https://www.digikey.com/product-detail/en/KC2520Z22.5792C1KX00/1253-KC2520Z22.5792C1KX00CT-ND/11610678/?itemSeq=329226141
The question is that the text above (shown on page 9) states that "The master clock (MCLK) should be synchronized with LRCK". So, how can I achieve such synchronization?
This is the basic schematic of the IC:
Another simple question is about the type of audio amplifier that is required to connect to the analog output... it should be class A, B, AB, H?