I'm trying to predict/handle the bit growth that occurs when implementing a complex multiplier using Gauss' method. I am looking to implement this multiplier in VHDL. The FPGA I use has a limited number of DSP elements, and so I anticipate that should I implement this multiplier correctly, it would reduce the number of DSP required per complex multiplication by 1.
Should A = (a+ib) have bit width m, and B = (c+id) have bit width n, then classically:
C = A x B = (a+ib) x (c+id) = ac - bd + i(ad + bc)
will have bit width of m + n + 1 for both its real and imaginary parts respectively.
Now, should I use Gauss' method of complex multiplication whereby only three multiplications are performed, namely ac, bd and (a+b)(c+d), then:
C = A x B = (a+ib) x (c+id) = ac -bd + i[(a+b)(c+d) - ac-bd], Here, we'd find that the real part will have a bit width of m + n + 1 as before, but the imaginary part will now have a bit width of m + n + 3.
Please can someone confirm whether this is really the case (I've checked a few times but could be wrong), and then further give me an idea as to how to handle the additional bit growth in the imaginary term (since I require that it have the same bit with as the real).
Thank you in advance.