My experience with the "electrical rules check" is it finds lots of false positives and relatively few true errors. Whether the few true errors it finds are worth the effort of digging through all the false-positives is context dependent.
It's quite common to use multiple pins in parallel on power ICs to increase current handling capacity without going to a weird package. If you see a power IC with two pins with exactly the same name then that is almost-certainly what is going on.
Whoever designed that schematic symbol doesn't seem to have been paying much attention though, "outs" is an input pin! That still doesn't solve your problem of having two output pins though.
Ultimately your choices come down to some combination of.
- Change the ERC rules to be less strict (but allowing two outputs to be connected together kind-of defeats the result of an ERC, so tat is not very useful in this case).
- Place No-ERC markers on the offending nets. You can create a "specific no ERC" marker for a particular violation from the right-click menu of the violation entry.
- Modify the schematic symbol, for example you could mark one of the two output pins as a "passive" pin (assuming your rules allow an output pin to be connected to a passive pin)
- Just ignore the errors.