I am designing a simple Buffer to get the voltage of a high-impedanze source to an ADC (60k Impedance). For that I choosed an JFET in the source-follower configuration.


simulate this circuit – Schematic created using CircuitLab

To bias the gate to ground and keep the input-resistance high, there will be an >1Meg Gate-Risistor.

I am a little bit confused about how to select the Source-Risistor, because the Output-Voltage (Voltage at the source) should be nearly independend of the load. So it should not matter, if I am using a 1k or 100k resistor, does it? Some resources say, with Rs, you bias the JFET.

Could someone please clarify this to me?

A second Question: To get better linearity, I may use a current Source at the Source (biasing the Gate to Vcc/2 with a single supply-voltage) What is the approach to choose a current for that?

Thanks for any advice

  • \$\begingroup\$ What input voltage does the A-to-D accept? Many accept voltage between ground and some +Vreference (often +Vdd), Others accept differential input voltages between two input pins. Still others have a +ve DC supply and -ve DC supply, and accept bipolar input voltage above and below ground. \$\endgroup\$
    – glen_geek
    Commented Jun 12, 2020 at 20:07
  • \$\begingroup\$ It's single ended 3V peak-to-peak. \$\endgroup\$
    – Feuerlink
    Commented Jun 12, 2020 at 20:19

2 Answers 2


Indeed, with \$R_S\$ you choose the DC operating point of the JFET. An n-type JFET will start conducting as soon as the voltage \$V_{GS}\$ between gate and source is higher than some negative pinch-off voltage \$V_P\$ that depends on the type of the transistor. From this point, the drain current will rise quadratically with \$V_{GS}\$,

\$I_D=I_{DSS} \left( 1-\frac{V_{GS}}{V_P}\right)^2 \$,

where \$I_{DSS}\$ is the drain current at \$V_{GS} =0\$. Therefore \$V_{GS}\$ is usually negative. Since the gate is at ground level (due to \$R_G\$), the source must be positive. This is done by \$R_S\$, since \$V_S = I_D\cdot R_S\$ and finally \$V_{GS} =-I_D\cdot R_S\$.

So \$I_D\$ depends on \$V_{GS} \$ and \$V_{GS}\$ depends on \$I_D\$ and on \$R_S\$. The value of \$R_S\$ for a given \$I_D\$ can be found either graphically or by solving the equation. Small changes in the transistor parameters (\$V_P\$, \$I_{DSS} \$) will not have a huge effect on \$I_D\$.

A simple recipe: Choose an \$I_D\$. For a source follower, a good starting point would be \$I_D\approx I_{DSS}/2\$. From the formula above (or from the characteristic curve of the transistor), determine \$V_{GS} \$. Finally, \$R_S=-\frac{V_{GS}}{I_D} \$ (remember that \$V_{GS} \$ will be negative).

However, with a source follower the gate is usually not set to 0 volts. Instead, a voltage divider is used to set the gate voltage so that the source terminal is at about half the supply voltage.

  • \$\begingroup\$ Why is the source follower gate usually not set to 0 volts? Does it have some negative effects?Because, the voltage divider would reduce the input resistance. It would be possible, to use very high values of resistors, but with that, the noise would also increase \$\endgroup\$
    – Feuerlink
    Commented Jun 13, 2020 at 14:23
  • \$\begingroup\$ @Feuerlink - Typically, the pinch-off voltage \$V_P\$ of a JFET is only a few volts. When the gate is grounded, the DC operating point of the source terminal is somewhere between \$V_P\$ and 0V. This would severely limit the large signal behavior of the circuit. \$\endgroup\$
    – Hufi
    Commented Jun 13, 2020 at 20:13

Negative feedback is in action so it takes a little bit of thought. So, let's talk about things happening in slow motion as a way of explaining how things start and settle down.

  • Current will pass through the JFET because the way the circuit is biased ensures that.
  • As drain/source current starts to flow, the source resistor drops voltage across it and the source voltage rises above 0 volts
  • As the source voltage rises, the DC voltage on the gate relative to the rising source can be regarded as becoming more negative relative to the source
  • This is because the gate is biased at 0 volts and the source voltage is rising
  • As the gate-source voltage becomes more negative the JFET starts to turn off and restricts the current flow into the source resistor
  • The J112 typical requires -1 volt between gate and source (\$V_{GS(OFF)}\$) to cut-off the drain-source channel to 1 uA but \$V_{GS(OFF)}\$ can be as high as -5 volt.

So, after all of this, the source settles at a voltage that satisfies the actual JFET used. It will be typically 1 volt higher than 0 volts but can be 2 or more volts if the source resistor is much bigger. Generally we can use formulas to calculate this but, like any type of FET, there is a lot more variation on how much the gate-source voltage needs to be for a particular FET compared to the more reliably predictable BJT. This renders the formulas a bit useless if you want precise predictions.

The current that will be flowing in the J112 will be around 3 mA (based on what the data sheet says) so, if you take a stab at 1 volts at the source, the resistor will be circa 330 ohm.


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