I need help if my SDC constraints are correct for a digitally noise filtered CLOCK and DATA inputs. I'm not sure if CLK3 grouping and create_clk CLK2 are correct. I would like to know on how to make a constraints of the following.

  1. Constraints for CLK3 (create/generated clock).
  2. Constraints for Input Delay of DATAIN.
  3. Constraints for Output Delay of DATAOUT with respect to CLK2, to guarantee the minimum Input Delay feeding the Master device which will be captured by CLK2 rising edge to insure enough hold time.

enter image description here

Note: The reason for using CLK3 as clock input of FF10 is to minimize power consumption because other than FF10, there are hundreds or even more than a thousand FF's after the filter circuit. CLK2 or CLK3 are not continuous, it will run only as needed and its frequency is much slower than the continuous CLK1 coming from the external oscillator.

create_clock -period 20 -name CLK1 -waveform {0 10} [get_ports CLK1]
create_clock -period 1000 -name CLK2 -waveform {0 500} [get_ports CLK2]
create_generated_clock -name CLK3 -combinational -source [get_pins FF4/Q ]

set_clock_groups -asynchronous -group [get_clocks {CLK1}] -group [get_clocks {CLK2 CLK3}]

# -min 80 due to CLK2 filtering
set_output_delay -clock [get_clocks CLK2] -min 80 [get_ports DATAOUT]
set_output_delay -clock [get_clocks CLK2] -max 90 [get_ports DATAOUT]

The expected timing should look like below. enter image description here

Any help would be appreciated. Thank you.


You have a logic clock of 50 MHz and a 1 MHz synchronous serial input consisting of CLK2 and DATAIN.

The function of the serial clock CLK2 is to indicate the timing for DATAIN as it travels across the serial bus. It is not to connect to the clock input of flip-flops in a logic circuit.

Your circuit should see serial CLK2 as a logic signal, just like DATAIN is. Serial CLK2 happens to be a square-wave control signal. At an agreed point within each serial CLK2 cycle, DATAIN will be steady and the data bit on it can be sampled. It is usually shifted into a shift register but you don't describe your application so I can't say.

Synchronous serial protocols reference their serial data stable periods and changing periods to an edge on their serial clock. Here, serial CLK2 is nice and slow compared to your logic clock CLK1, which has a 50:1 clock speed advantage over it. Your receiver needs to detect a rising or falling edge on serial CLK2 to find a reference point. This all takes place after your input filter circuit. A rising edge is a 1 from your CLK2 filter that was preceded by a 0, while the opposite is a falling edge.

Just to complete the picture, if a circuit has to sample synchronous serial data at a later phase of the serial clock period, it can detect the edge then delay by a number of logic clocks to reach a particular point in the serial clock cycle phase before taking a serial data bit. But it's unlikely you'll need that here.

Your input filter circuit is fine but the part beyond needs redesigning to meet these changes. Please remember that throughout your synchronous logic circuit, the only clock going to flip-flops or registers is logic clock CLK1. Do not clock anything from CLK2.

Your SDC file now doesn't need clock constraints on CLK2 because it isn't a circuit clock. It will need a constraint on each of CLK2 and DATAIN from the input pin to first register path delay, which you can find.

  • \$\begingroup\$ The purpose for not using a usual shift register on DATAIN is because it is assumed that there will a noise spike on it, that is the reason why a filter is used. I have added a timing diagram to my question and I need help on how to create constraint for output delay of DATAOUT with respect to CLK2 since CLK3 is a filtered (delayed) CLK2 and it drives the DATAOUT at FF10's Q output. Also, I need help on to constraints the input delay. \$\endgroup\$
    – zeahr
    Jun 13 '20 at 8:20
  • \$\begingroup\$ @zeahr, please re-read my answer, your comment reads like you haven't understood much of it. Particularly the part saying: only logic clock CLK1 goes to the clock input of a flip-flop. CLK2 is not a logic clock and does not get clock constraints. All these are some the fundamentals of synchronous logic design that make simple and reliable circuits. \$\endgroup\$
    – TonyM
    Jun 13 '20 at 8:55
  • \$\begingroup\$ I understand that CLK2 is not a logic clock and does not get a clock constraints, but in FF10 (pink FF) the clock input is CLK3 which is a delayed CLK2 (as a data) driven by CLK1. I would like to know how to constraint the CLK3? The reason why CLK3 is used in FF10 instead of detecting the rising edge of CLK2 using CLK1, is because I need the power consumption as low as possible. In the actual circuit there are many FF's after the Filter circuit and if I will use CLK3 the toggling will be fewer because CLK2 is not always running while CLK1 is coming from an oscillator and always running. \$\endgroup\$
    – zeahr
    Jun 13 '20 at 9:26
  • \$\begingroup\$ Also, I want to create a constraint that will guarantee a minimum output delay with respect to CLK2 because that will be the minimum input delay of the device receiving the DATAOUT which generates the CLK2. \$\endgroup\$
    – zeahr
    Jun 13 '20 at 9:29
  • \$\begingroup\$ @zeahr, if you add edge detection on CLK3, you can use it as an enable for FF10, which is then CLK1 synchronous like everything else. Otherwise, the relationship of the FF10 output to CLK1 is not well defined. \$\endgroup\$ Jun 13 '20 at 10:07

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