I am referring to datasheet of LM3743 block diagram in Pg no. 5


The EA and PWM Comp is in leading edge modulator configuration. According to my understanding SR latch which comes after PWM Comp must be R (Reset) must be triggered by Clock and S (Set) must be output of PWM Comp.

Example below gives better understanding.


Which determines duty cycle on time of Vx or off time in figure b ? What are these configurations called in industry (keyword) ?

Should IL (Inductor current) should have raise during off time of Vx (Figure b) or fall from peak value during off time Vx (Figure b)

Further latch output Vx (Figure b) is given to gate driver high side and low side.


There are various types of modulation schemes whose choice depends on the end application. The most common type is the trailing edge modulator. In this type, the on-time is initiated by the clock why the loop sets the event at which the switch turns off. The below circuit shows a typical industrial implementation in an integrated circuit for both voltage- and current-mode control:

enter image description here

This is an excerpt of the seminar I taught at APEC in 2019.

The second type is called leading-edge modulation. In this approach, the clock sets the turn-off time why the loop set the events at which the turn-on occurs within a switching cycle. This technique was popular in so-called magnetic amplifiers, commonly known as mag-amps and implemented in the PC silver boxes (power supplies) for multi-output solutions. More more modern solutions known as mag-amps killers were released and also based on leading-edge modulation. They are described page 866 in the book I published in 2014.

Finally, the dual-edge modulation is implemented in high-speed dc-dc converters used in motherboards or graphic cards where reaction speed is key: in the trailing-edge approach, when the switch has turned off, you have to wait for the end of the cycle so that the next clock initiates a new turn-on. Same with the leading-edge scheme where you can't turn off before the clock occurs. As you can see, reaction speed in case of under- or over-shoot is at stake and can affect performance in highly-demanding applications where the over- and under-shoots must really be minimized. The below picture gives an overview of these techniques:

enter image description here

  • \$\begingroup\$ Leading edge that I am assuming in datasheet( assuming due to error amp and pwm comparator configuration), i.e. ramp behavior is not as you explained it. Are there many ways of using modulator (PWM mod, sr latch)?. Above topology of ramp sweeps between 1.2 to 2.2V so there is 1.2V offset ?. Bit curious on clamp voltage of Error Amplifier if ramp sweeps from 0 to 1V (1V ramp as datasheet) my clamps would be >0 and <1 approx where can I find it in DS ? \$\endgroup\$ – Pai Jun 17 '20 at 18:22

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