# Understanding Diode ROM

I read that the intersection of a row and column represents a bit, and if an intersection is linked with a diode the corresponding data output line goes low or 0. But why?

Take the following figure for example. An input of $$\ A_2 A_1 A_0 = \{0, 0, 0\}\$$ gives a 0 (LOW) out of a's NAND gate and 1 (HIGH) out of b-h's NAND gate. The low potential of a's NAND gate sinks all current in the circuit, and there will be four parallel currents from $$\ 5V \$$ voltage supply, each through $$\ R_3, R_2, R_1, R_0 \$$ into a's NAND gate. For $$\ D3 \$$ to be 1 (pulled HIGH), the impedance of a's NAND gate has to be significantly larger than $$\ R_3 \$$ keeping $$\ D_3 \$$ at a potential close to $$\ 5V \$$.

Current through $$\ R_2 \$$ will then get a diode voltage drop (e.g. -0.6V) before reaching a's NAND gate. Assuming all four pull-up resistors have the same value, then voltage difference between $$\ D_3 \$$ and $$\ D_2 \$$ is just that diode voltage drop (i.e. 5V vs. 4.4V), but a 4.4V will not get interpreted as a LOW (0). So instead of outputting 1011, I should get 1111.

Above is my interpretation which make sense to me, but it got to be wrong.

To output 1011, there has to be no current through $$\ R_3, R_1, and R_0 \$$, pulling $$\ D_3, D_2, and D_0 \$$ to HIGH (5V), leaving only current running through $$\ R_2 \$$ and the diode into a's NAND gate. The voltage drop of $$\ R_2 \$$ and the diode takes $$\ D_2 \$$ low. This has to be what's happening but nothing sense to me: a's NAND has the lowest potential in the circuit and sinks all current through all four pull-up resistors.