# BCD Bi-directional counter with variable counting speed in proteus

I am working on a project. And its description is: Design a 3-digit counter which should has 4 buttons (up, down, right, left).

with pressing the up button the counter should up-count for 5 seconds (each count last 1 second) and after the 5s the counting speed should be doubled and this continues doubling the speed after each 5s till the operating speed reaches 128 then it operates with 128x to the end (for example if we start with 1Hz the final frequency should be 128Hz).

With pressing the down button the above scenario will be reversed (if start with 128Hz we should end up with 1Hz).

with pressing the right button the counter should up-count one-by-one normally. with pressing the left it should acts opposite to the right button.

I started with 74ls192 counter, a frequency doubler (https://i.stack.imgur.com/ViirF.png), frequency divider, etc.

The left and right buttons are trivial. However i had problem with implementing the up and down buttons. i'm thinking of placing a clock generator before them and place a frequency doubler after it then connect it to up-pin in 74ls192. and for down- button we place a frequency divide by 2 circuit then connect it to the IC. I dont know how to manage them with 5seconds.

I implement the following: COUNTER FULL the problem is it does not work? where i doing wrong?

and inside each Block is something like this: 74ls192

So could you please guide me to solve this problem? Or how to start tips.

P.S: it is also required to design every single function with only logical gates. (so i have implemented 74ls192 by gates myself from http://www.datasheetcafe.com/sn74ls193-datasheet-pdf/) and even flip flops (which took a lot of time )

Any help will be greatly appreciated.

• You never actually stated what the problem was that you had. You never drew your circuit where you got to. Jun 13, 2020 at 15:26
• Its a bit messy. I'll add it to the post. Jun 13, 2020 at 15:37
• 74LS192 is a 4 bit counter. With the kind of 128x clock you are talking about, I hope you have the idea that the counter will overflow after every 16 clock cycles. Jun 18, 2020 at 6:25
• Why do you implement 74LS192 using gates? What kind of free time have you got? ;-) Jun 18, 2020 at 6:31
• It wasn't intended. our instructor want it to be a challenge... Jun 18, 2020 at 7:11