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I was reading a textbook which syas:

In asynchronous transmission, we send 1 start bit (0) at the beginning and 1 or more stop bits (1s) at the end of each byte. There may be a gap between bytes.Asynchronous here means “asynchronous at the byte level,” but the bits are still synchronized; their durations are the same. enter image description here

I am a little bit confused here, what does bits are still synchronized mean? how does bits gets synchronized and whom those bits gets synchronized to?

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  • \$\begingroup\$ maybe, just a maybe, it means that at each clock pulse, a bit will be sent/received but a byte will take 8+2(start-stop) = 10 clock pulses to be counted as sent/received, so, it might be considered asynchronous with clock. As i said, just a maybe. \$\endgroup\$ – muyustan Jun 14 at 15:08
  • \$\begingroup\$ uh, that textbook wording is so confusing, I'd call it "borderline wrong". \$\endgroup\$ – Marcus Müller Jun 14 at 15:31
  • \$\begingroup\$ Yes, it's a very bad explanation. There is no such thing as "gap between data bits" in asynchornous transmission. \$\endgroup\$ – Fredled Jun 14 at 15:36
  • \$\begingroup\$ With serial/uart you certainly may have gaps between data units, no reason for it to be continous all the time. Between bits no, but as shown in the image, "may" between "data units" yep. \$\endgroup\$ – old_timer Jun 14 at 18:22
  • \$\begingroup\$ "bits are still synchronized" is poorly written. \$\endgroup\$ – old_timer Jun 14 at 18:24
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I find that textbook description very confusing.

The sender of the data is generating a clock which determines where the edges of the bits are.

The receiver generates its own clock which determines, in simple terms, when we sample the data stream to get the correct bit values. This clock will not be synchronised with the senders clock, even if it starts off synchronised the frequency will be a little off and it will drift over time.

So the receiver re-synchronises its clock every byte by sensing the edge of the start bit. This means that the bits in a byte are synchronised and they are synchronised to the start bit.

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  • \$\begingroup\$ In a normal receive UART, its clock never alters i.e. it doesn't get re-synchronized by the fall of the start bit. What evidence have you that this actually happens in the vast majority of standard UARTs? Also, there is no need to re-sync because sampling is done at a significantly higher clock rate than the data. Also when you say this The receiver generates its own clock which determines, in simple terms, when we sample the data stream to get the correct bit values - that is not particularly true - the clock is free running and it is the logic of the UART that detects the start bit and... \$\endgroup\$ – Andy aka Jun 16 at 12:49
  • \$\begingroup\$ ... there are counter circuits that decide when the data stream is sampled. So, unless you have evidence to the otherwise, you are misdirecting the questioner (@amjad) IMHO. \$\endgroup\$ – Andy aka Jun 16 at 12:51
  • \$\begingroup\$ Note the "in simple terms" statement. I am well aware of how this is done in detail. I was not misdirecting the questioner simply trying to keep it simple. There are multiple nuances to this the sample clock is usually produced by a DPLL and sampling is not always just done once. \$\endgroup\$ – RoyC Jun 16 at 15:36
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At the instant the start bit arrives the receiver knows only one thing; the nominal time duration of one bit. The receiver has its own clock running at typically 16 times higher than the expected data rate and, these come together in the picture below: -

enter image description here

So, in the above picture, the receive UART counts 8 clock cycles from the instant that the start bit falls to zero. After 8 clock cycles, it knows it is approximately in the centre of the start bit.

From that point it counts 16 clock cycles to position itself at the approximate centre (mid-bit) of the first bit. It then samples that data and restarts the clock counter and, another 16 clock cycles later it will be in the position of the 2nd bit and it samples that bit.

This continues until all the bits of the UART transmission byte have been received.

how does bits gets synchronized and whom those bits gets synchronized to?

Bit sampling is synchronized to the falling edge of the start bit and the receiver assumes that its clock (and the clock of the transmitting UART) are fairly well matched. There can be a little drift and because the byte length is quite small this doesn't erroneously position the mid-bit too far off but, if clocks continue to drift relative to each other (or the baud rate changes) then this type of transmission will fail.

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    \$\begingroup\$ "The receiver has its own clock running at approximately the the same speed as the data but many times higher, usually 16 times higher: " I am lost in this sentence \$\endgroup\$ – muyustan Jun 14 at 15:39
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    \$\begingroup\$ @muyustan yeah that was good old fashioned gobbledygook and now fixed. \$\endgroup\$ – Andy aka Jun 14 at 15:41
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    \$\begingroup\$ don't know what gobbledygook is but made me laugh :D \$\endgroup\$ – muyustan Jun 14 at 15:42
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    \$\begingroup\$ I've hyper linked it LOL. \$\endgroup\$ – Andy aka Jun 14 at 15:43
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Asynchronous means that the two devices don't share a common clock.

In synchronous communication, one of the devices would output a clock in addition to the data. The receiver of the clock would use that clock to determine when to set the bits to the appropriate level.

In asynchronous communication, the two devices are configured in a common way without sharing a clock. In UART, that is what the 115200/8/N/1 configuration is for. It tells the device how to transmit and when to expect data. The side effect of this is that each device has to generate its own clock and they have to be pretty close together in frequency. If they are too far off, then you'll sample/transmit at the wrong time.

The start/stop bits are just used to indicate when the data starts and ends.

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When transmitting discrete symbols, you always need some kind of symbol or (in the case of binary symbols) bit synchronization. Otherwise the receiver wouldn't know when to make the decision about the transmitted symbols.

In the case of asynchronous transmission, there will be a start bit, marking the start of a packet of bits (often called frame or byte). Based on this start point, the receiver may estimate the timing of the subsequent bits, since the bit duration is known. This works as long as the clocks of transmitter and receiver do not differ greatly and as long as the number of bits is not too large.

Since the interval between a stop bit and the subsequent start bit can be anything between 0 and infinity, this is called asynchronous transmission. As soon as the start bit has been detected, the data bits follow with a well-defined interval, the bit duration.

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If the symbols are synchronous, then that system is a synchronous system, according to any definition I can think of.

The fact that there's need for a start bit to mark a word doesn't change that.

I'll plainly say that your textbook is simply wrong (that happens!).

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  • \$\begingroup\$ symbols are OR symbol is ? \$\endgroup\$ – muyustan Jun 14 at 15:43
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This is not an answer.

The image presented in the question should look more like this.

enter image description here

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