# Sizing of different PCB polygons on different layers for high current

I need to design some traces or polygons for high current (15A) on a 4 layer Lithium Battery Management System board, but I am unsure about their sizing.

I am following a reference design from TI, from which the screenshots of the PCB below are taken. The board is a Lithium Battery Management Solution (https://www.ti.com/tool/TIDA-00982).
My question is general ,but I use this board as an example.

The red marked polygons go to a Lithium Battery positive terminal with 15A continuous current. The narrowest side of the polygons is 3.5mm on top and second inner layer, 2mm on the bottom layer (no connection on first inner layer).
I'm trying to understand how they calculated the sizes of those polygons.

I can order only 0.5 oz inner layers and 1 oz for external, so I probably need to increase the size of those polygons.

I thought: the polygon on the top layer is fixed due to other components, but I can increase the polygon on the second inner layer and bottom one (connected through multiple vias).
The problem is how much?

If you have two mirrored traces between the same points, on two different layers, the current will be halved. What if you have different polygon sizes and on different layers (externa/internal)?

Should I calculate like below?

• current per polygon: 15A / 3 polygons = 5A per polygon
• top layer polygon size (fixed): 3.3mm --> use Trace Width Calc with 5A, 40C temp rise, 1oz copper --> 1.2mm trace width for external layer-->top layer is ok
• inner layer 2 polygon size: use Trace Width Calc with 5A, 40C temp rise-->6.2mm trace width for internal layer
• bottom layer polygon size: use Trace Width Calc with 5A, 40C temp rise, 1oz copper --> 1.2mm trace width for external layer.

Now that I have the width of the polygons, what about the length? Does the length not matter for heat dissipation? Is length decided by the requirement (in this board) “short low impedance connections for power connection”?