# STM32F429ZI ADC converting too fast

I am trying to trigger ADC1 to convert (for the moment) one channel of a STM32F429ZI microcontroller (on the Nucleo Board) by TIM2 every second. With the code below I configured 180 MHz core frequency, a timer underflow every second (working), the ADC to convert channel 3 with 480 ADC clock cycles (@22.5 MHz) sample time and 12 bit resolution. So with the abovementioned configuration I would have expected ~22 µs conversion time of the ADC.

To check for the conversion time I need to use Segger SystemView as I don't have an oscilloscope. Contrary to my expectation the ADC interrupt service routine (ISR 34) is called 2.6 µs after the timer interrupt (ISR 44)

Can someone explain why the ADC is converting so fast?

Code:

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File    : main.c
Purpose : Generic application start

*/

#include <stm32f4xx.h>
#include "SEGGER_SYSVIEW.h"

void ClockInit(void)
{
uint32_t timeout = 1000000;

// enable flash prefetch
FLASH->ACR |= FLASH_ACR_PRFTEN;
// set 5 wait states (needed for high PLL frequency)
FLASH->ACR &= ~FLASH_ACR_LATENCY_Msk;
FLASH->ACR |= FLASH_ACR_LATENCY_5WS;
do
{
timeout--;
} while (((FLASH->ACR & FLASH_ACR_LATENCY_Msk) != FLASH_ACR_LATENCY_5WS) && (timeout > 0));

// switch on external clock, bypass HSE with it and wait for clock to be ready
RCC->CR |= (RCC_CR_HSEON | RCC_CR_HSEBYP);
timeout = 1000000;
do
{
timeout--;
} while (((RCC->CR & RCC_CR_HSERDY_Msk) != RCC_CR_HSERDY) && (timeout > 0));

// configure (HSE as clock source, M = 4, N = 180, P = 2), enable and wait for PLL
RCC->PLLCFGR = (RCC_PLLCFGR_PLLSRC_HSE | (4 << RCC_PLLCFGR_PLLM_Pos) | (180 << RCC_PLLCFGR_PLLN_Pos));
RCC->CR |= RCC_CR_PLLON;
timeout = 1000000;
do
{
timeout--;
} while (((RCC->CR & RCC_CR_PLLRDY_Msk) != RCC_CR_PLLRDY) && (timeout > 0));

// configure rest of clock tree
RCC->CFGR &= ~(RCC_CFGR_PPRE2_Msk | RCC_CFGR_PPRE1_Msk | RCC_CFGR_HPRE_Msk);
RCC->CFGR |= (RCC_CFGR_PPRE2_DIV2 | RCC_CFGR_PPRE1_DIV4 | RCC_CFGR_HPRE_DIV1);

// set PLL as clock source and wait until clock is ready
RCC->CFGR &= ~(RCC_CFGR_SW_Msk);
RCC->CFGR |= RCC_CFGR_SW_PLL;
timeout = 1000000;
do
{
timeout--;
} while (((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_PLL) && (timeout > 0));

SystemCoreClockUpdate();

// enable GPIOA, ADC1 and TIM2 clocks
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;
}

void TimerInit(void)
{
// counter direction down, generate update event only on underflow
TIM2->CR1 |= (TIM_CR1_DIR | TIM_CR1_URS);
// set update event as trigger source
TIM2->CR2 &= ~TIM_CR2_MMS_Msk;
TIM2->CR2 |= TIM_CR2_MMS_1;
// enable update interrupt
TIM2->DIER |= TIM_DIER_UIE;
// set timer and reload value for update generation every 1000 ms
TIM2->ARR = TIM2->CNT = 90000000;
}

void TimerStart(void)
{
TIM2->CR1 |= TIM_CR1_CEN;
}

{
GPIOA->MODER |= GPIO_MODER_MODE3;
// set clock prescaler to 4 -> 22,5 MHz
// enable timer 2 trigger event as start trigger on rising edge and generate EOC interrupt after each conversion
// set 480 cycles sample time for channel 3
// set channel 3 as first (any only) regular channel
// enable EOC interrupt
}

void InterruptInit(void)
{
// Timer 2
NVIC_SetPriority(TIM2_IRQn, 3);
NVIC_ClearPendingIRQ(TIM2_IRQn);
NVIC_EnableIRQ(TIM2_IRQn);
}

void TIM2_IRQHandler(void)
{
SEGGER_SYSVIEW_RecordEnterISR();
NVIC_ClearPendingIRQ(TIM2_IRQn);
TIM2->SR &= ~TIM_SR_UIF;
}

{
uint16_t Value;
SEGGER_SYSVIEW_RecordEnterISR();
}

int main(void)
{
ClockInit();

SEGGER_SYSVIEW_Conf();

TimerInit();