# Finding common mode level and max output swing in two stage op-amp

I just want a hint on how to even start attempting this question. I wasn't able to link any equation to the given values in the question. Felt like too much was unknown.

Indeed, the task data are incomplete or at least formulated tacitly -- depends on the context of your project. The design uses short channel MOSFETs (lenth < 2u), but if you absolutely need to attempt this task, you can start and replace transistors with the simplest MOSFET model (longchannel and without channel length modulation) as a voltage controlled current source (similar to technique used in an answer to this question)

simulate this circuit – Schematic created using CircuitLab

I_DS = 0 V_GS < V_Thresh

I_DS = beta·(V_GS – V_Thresh – V_DS/2)·V_DS V_GS > V_Thresh , V_DS < V_DSAT

I_DS = (beta/2)·(V_GS – V_Thresh )^2 V_GS > V_Thresh , V_DS > VDSAT

 V_DSAT = V_GS – V_Thresh

For pMOS, change signs to accommodate device polarity.

beta = u0 (carrier mobility) * Cox (oxide capacitance) * W/L

You can find V_Thresh, u0, and Cox parameter values in reference documents, e.g. Star-HSpice Manual.

Typical V_Thresh are 0.45V for nMOS and 1V for pMOS; the default u0 are 2.0718e-5 (NMOS) and 8.632e-6 (PMOS), Cox about 0.00035 Farade/square meter.

If you succeed in this undoubtedly useful exercise, you can further attempt more advanced transistor models.

A regular approach to analysis of electronic designs is the use of simulators (SPICE/PSPICE/HSPICE, Cadence Spectre X simulator, Mentor AMS simulator, other high-end packages and numerous free tools).