# '1011' Overlapping (Moore) Sequence Detector in Verilog

I'm designing a "1011" overlapping sequence detector, using Moore Model in Verilog .

The FSM that I am trying to implement is as shown below :-

Verilog Module :-

timescale 1ns / 1ps

module seq_detector(
input x,clk,reset,
output reg z
);

parameter S0 = 0 , S1 = 1 , S2 = 2 , S3 = 3 , S4 = 4;
reg [1:0] PS,NS ;

always@(posedge clk or posedge reset)
begin
if(reset)
PS <= S0;
else
PS <= NS ;
end

always@(PS or x)
begin

case(PS)
S0 : begin
z <= 0 ;
NS <= x ? S1 : S0 ;
$display(PS); end S1 : begin z <= 0 ; NS <= x ? S1 : S2 ;$display(PS);
end
S2 : begin
z <= 0 ;
NS <= x ? S3 : S0 ;
$display(PS); end S3 : begin z <= 0; NS <= x ? S4 : S2 ;$display(PS);
end
S4 : begin
z <= 1;
NS <= x ? S1 : S2 ;
$display(PS); end endcase end endmodule Testbench :- timescale 1ns / 1ps module testbench; // Inputs reg x; reg clk; reg reset; // Outputs wire z; // Instantiate the Unit Under Test (UUT) seq_detector uut ( .x(x), .clk(clk), .reset(reset), .z(z) ); initial begin clk = 1'b0; reset = 1'b1; #15 reset = 1'b0; end always #5 clk = ~ clk; initial begin #12 x = 0;#10 x = 0 ; #10 x = 1 ; #10 x = 0 ; #12 x = 1;#10 x = 1 ; #10 x = 0 ; #10 x = 1 ; #12 x = 1;#10 x = 0 ; #10 x = 0 ; #10 x = 1 ; #12 x = 0;#10 x = 1 ; #10 x = 1 ; #10 x = 0 ; #10$finish;
end

endmodule

Simulation Output :-

The issue is that, the output 'z' is staying low always, even when I've applied an input sequence which has three '1011' patterns in it . What's the possible modification that I'd have to do, so as to eliminate this error ?

• This seems to be almost a duplicate of your previous question with exactly the same title. Can you edit to explain the difference and modify the title to show the difference. If not this is likely to be closed as a duplicate. Jun 16 '20 at 6:12
• The state machine(previous was a Mealy design, whereas this is Moore) is different , and the error issue is different . The issue pointed in previous post, has been rectified in this (non-blocking assignment), but still the issue persists. Jun 16 '20 at 6:20
• The title edit makes it very clear. Thanks. Jun 16 '20 at 6:23

In Moore Machines the output depends only on the current state. So when you are changing your output, (z in this case), the sensitivity list should be only the current state.

You should add the default case so that your FSM remains idle when there is no change in the current state.

In your combinational block, you should use blocking statements to prevent your simulation from running into infinite loops and getting locked up.

Simulate the circuit here on my eda playground:

Design:

timescale 1ns / 1ps

module seq_detector(
input x,clk,reset,
output reg z
);

parameter S0 = 0 , S1 = 1 , S2 = 2 , S3 = 3 , S4 = 4;
reg [2:0] PS,NS ;

always @(posedge clk or posedge reset)
begin
if(reset)
PS <= S0;
else
PS <= NS ;
end
always @(PS, x)
begin
case(PS)
S0 : begin
NS = x ? S1 : S0 ;
$display(PS); end S1 : begin NS = x ? S1 : S2 ;$display(PS);
end
S2 : begin
NS = x ? S3 : S0 ;
$display(PS); end S3 : begin NS = x ? S4 : S2 ;$display(PS);
end
S4 : begin
NS = x ? S1 : S2 ;
$display(PS); end default: NS = S0; endcase end always @(PS) begin case(PS) S4: z = 1; default: z = 0; endcase end endmodule Testbench: timescale 1ns / 1ps module testbench; // Inputs reg x; reg clk; reg reset; // Outputs wire z; // Instantiate the Unit Under Test (UUT) seq_detector uut ( .x(x), .clk(clk), .reset(reset), .z(z) ); always #5 clk = ~ clk; initial begin$dumpfile("dump.vcd");
$dumpvars(1, testbench); fork clk = 1'b0; reset = 1'b1; #15 reset = 1'b0; begin #12 x = 0;#10 x = 0 ; #10 x = 1 ; #10 x = 0 ; #12 x = 1;#10 x = 1 ; #10 x = 0 ; #10 x = 1 ; #12 x = 1;#10 x = 0 ; #10 x = 0 ; #10 x = 1 ; #12 x = 0;#10 x = 1 ; #10 x = 1 ; #10 x = 0 ; #10$finish;
end
join
end
endmodule

`

Waveform:

https://www.edaplayground.com/w/x/kk

• Please don't hand out solutions to questions that are obviously homework. We don't want this site to become a homework answering service. Generally we prefer to give hints that guide the OP to finding their own solutions. Jun 16 '20 at 12:44
• Also, non-blocking assignments are usually not recommended for combinational logic such as your next-state and output blocks. The @(*) event list is also preferred for combinational logic because it is less error-prone. Jun 16 '20 at 12:51
• @ElliotAlderson, regarding answering homework questions, I don't answer them unless the asker has shown efforts. I follow the guidelines outlined in this answer electronics.meta.stackexchange.com/a/87/238188 Jun 16 '20 at 13:23
• Are you saying that we should not question the recommendations made by someone with a PhD? Here are recommendations from someone who wrote Verilog code professionally: sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf Jun 16 '20 at 14:07
• Using @(*) would not have changed the behavior in any way...it would still be a Moore FSM. Rather, it would have made the simulation behavior consistent with the hardware behavior, and avoids the occasional error of forgetting to include all necessary signals in the event list. Synthesis tools typically ignore the event list for combinational blocks. Jun 16 '20 at 17:13

Your state variable is too small. You have 5 states, but your variable is only 2 bits wide. It must be at least 3 bits wide. Change:

reg [1:0] PS,NS ;

to:

reg [2:0] PS,NS ;

Now I see z go high 3 times.

Now that you have unused states (5-7), you should add a default to your case statement.