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See the document here.

I am interested on using external interrupts, and trying to configure NVIC at register level. The statement below, which can be found in page 215, confused me:

Each priority field holds a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. The processor implements only bits[7:4] of each field, bits[3:0] read as zero and ignore writes.

Especially the bold part.

If that explanation was not present, I would directly think that I can write any number (0-255) to those 8 bit fields to set the priority. But now, I am confused such that whether I can use bits [3:0] or not.

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  • \$\begingroup\$ the written values in range of 0 to 255 are 'mapped' to 16 priority vales by ignoring 4 lower bits. \$\endgroup\$ – Juraj Jun 16 '20 at 12:23
  • \$\begingroup\$ @Juraj how about writing 128 and 129 ? They both translate(mapped) to 8? \$\endgroup\$ – muyustan Jun 18 '20 at 10:15
  • \$\begingroup\$ not to 8. to 128. \$\endgroup\$ – Juraj Jun 18 '20 at 12:01
  • \$\begingroup\$ @Juraj ok, considering left most 4 bits, they both will be 8. Then they have the same priority although I intended to make them different (128 and 129) \$\endgroup\$ – muyustan Jun 18 '20 at 12:46
  • \$\begingroup\$ you can't. the datasheet says they are the same priority. \$\endgroup\$ – Juraj Jun 18 '20 at 12:48
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Since the MCU implements 4 bits out of 8, you have 16 priorities and they are stored in high 4 bits of the 8 bit value. So you may not use the 4 lowest bits (unless you always keep them zero that is).

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  • \$\begingroup\$ I've been thinking about this for a while, so far, I understood that I can only have 16 different levels of priority between all interrupts. I accepted this. But, is there a specific reason why it is not implemented in the lower 4 bits instead of higher 4 bits which would make a lot more sense(in my opinion, at least) ? \$\endgroup\$ – muyustan Jun 19 '20 at 17:33

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