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Is there a way to annotate decoupling caps in the Eagle PCB schematic, such that in board layout, the airwires (or some other thing) make it clear which IC it's 'supposed to be near'? Right now the airwires just give me a line of caps all between supply and ground, so I have to work out which cap is for which IC.

Of course they are mostly the same value caps, and I could figure this out with naming. But if I had a device with many supplies and lots of decoupling needed, it seems like this would be a pain, so I'm wondering if there is some smarter way to do this.

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  • \$\begingroup\$ Just make a table on your schematic and refer to that table when placing decouplers as you might refer to any resistor or transistor or chip on the schematic when laying out a circuit board. \$\endgroup\$ – Andy aka Jun 16 at 12:31
  • \$\begingroup\$ I don't think this is a feature of many PCB and I have never seen it in Eagle. I usually print a copy of my schematic and hand place my components referring to that marking each component I have placed with a highlighter on the print. I will then track the board again manually to ensure I place the critical paths first. \$\endgroup\$ – Warren Hill Jun 16 at 13:52
  • \$\begingroup\$ You can create a special footprint including the footprint of the cap near the ic. But it reduces flexibility, if you want to move only the cap.But both will rotate together. It will also not figure in the net list as two components will be shown as one. \$\endgroup\$ – Fredled Jun 16 at 17:30
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As far as I'm aware, Eagle does not have this function. Two suggestions:

  • Place the capacitors explicitly on the IC's power pins, rather than on a separate power net. This can make your schematic quite cluttered.
  • On the schematic, place a box around the IC and the associated capacitors.

Neither will prevent you from placing them far away but do make the intent clearer, which is ultimately the goal of a good schematic.

Altium Designer has the concept of Rooms, which allows you to create a group of components that are associated but independent - this is probably the closest to what you want.

One final suggestion: for each IC, place a jumper from the global supply to an individual power net. This would allow you to have separate power nets for each IC that would stay attached. This might complicate ERC, and would introduce an extra footprint (although you could make this footprint a testpoint for a DFT bonus!).

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