The circuit below is from this App Note.

The document describes:

The capacitors C1 and C2 need to fully charge for the circuit to function properly. The definition of fully charged can vary depending on the accuracy required for the circuit. If we assume a 12 bit system the time required to fully charge the input capacitors is given below.

For 12 bit settling

τ1 = R1C1 = (1kΩ)(10μF) = 0.01s

T1 = ln(2^N)τ1 = ln(2^12) (0.01s) = 0.083s

In the second picture, when the switch is open R1 is about 63k. I want to understand better what really happens here when I use this circuit connected to an ADC. In my case I have a 12 bits ADC, so:

τ1 = R1C1 = (63kΩ)(10μF) = 630ms

T1 = ln(2^N)τ1 = ln(2^12) (620 ms) = 5.24s

5.24s is way too long. Does this mean I wouldn't sample the signal correctly until the capacitor charges in ~5s?

enter image description here

enter image description here

  • \$\begingroup\$ Your answer should be in milliseconds, not seconds. For 10uF/62K I get a basic time constant of 682mS. F = 1/0.682 = 1.466HZ. R would have to be 500K to get the time you calculated. Your initial results were in mS, so did you loose track of the decimal point? \$\endgroup\$ – user105652 Jun 17 at 0:42
  • \$\begingroup\$ Your schematic is hard to decipher. What is +3V3? Supply voltage? What an inverted input is connected to? What is the part at the nearest node to the left of pin 3? Between an opamp pin 3 and C16? \$\endgroup\$ – V.V.T Jun 17 at 4:53
  • \$\begingroup\$ 3.3V is supply voltage and Non Inverting pin is connected to Vcc/2 or 1.65V. \$\endgroup\$ – Blue_Electronx Jun 17 at 4:58
  • \$\begingroup\$ Your design uses a unity gain inverting configuration. To guarantee stability, you use a capacitor C17 (capacitance not specified in your drawing) in the feedback loop. Why do not use a recommended configuration of ADC driver with OPA376? Section 8.1.3 Driving an Analog-to-Digital Converter, ti.com/lit/ds/symlink/opa376.pdf? And why your sacrifice precision when lowering supply voltage to 3.3V? \$\endgroup\$ – V.V.T Jun 17 at 5:53

C18 is a blocking capacitor. The gain in this configuration is

abs(Gain) = 1/(1+1/(ω∙RC)^2)

Quite contrary to your fears, not fast, but slow changing signals, with the characteristic frequencies less than 6.28/((R14+R15)∙C18) ≈ 10 Hz, are filtered out.

The configuration you used is an AC Coupled Inverting Amplifier. For precise DC measurements, use the recommended ADC driver of the TI OPAx376 document, Section 8.1.3 Driving an Analog-to-Digital Converter.

| improve this answer | |

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.