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This is more of a computing question, but only electronics geeks would know such things. Today's computers use multiple layers of memory in order to work with data quickly. Currently CPU speeds are anywhere from 10 times to 100 times faster than RAM memory. Therefore, CPUs are built with a small amount of very fast memory (Static RAM, or SRAM) which is usually from 10 KB to 10 MB in size. Data cached in this memory is the fastest to work with and DDR RAM is usually much slower (10-100 times).

Wikipedia says DDR3 RAM currently takes 5-10 ns per "cycle". What does this mean exactly, and how fast is SRAM in comparison? Also, for embedded projects utilizing FPGA's, how useful is SRAM and DDR3 and can either be omitted in favor of the other? (eg. No need of SRAM if DDR3 speeds are similar)

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Cycle as used on that web page means "clock cycle": the time taken for one pulse of the clock signal used by the ram. So the 100MHz clock corresponds to a 10ns cycle.

Internally, this corresponds to selecting a row within the chip and reading the corresponding column lines; this brings out a set of values (let's say 256 bits = 8 bytes), for each of the 8 chips on the RAM.

There then follows a response burst where the values are transferred back to the processor. The bus is 64 bits wide, so there will be several transfers. Usually this fills an entire cache "line".

(Note that there is an implicit pipeline: you can send out another request before the first has finshed)

For an FPGA project, you'd use onboard SRAM in preference, but if there isn't enough or you need to share it, you would use external DDR RAM.

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  • \$\begingroup\$ Great info, but how does this compare specifically to DDR3 RAM? Do you know like how many times faster/slower would DDR3 RAM be in comparison? Or is it apples to oranges? \$\endgroup\$ – Robinicks Dec 5 '12 at 16:55
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    \$\begingroup\$ Well, if you want specifics you have to be specific about the SRAM - link a datasheet to the FPGA you're interested in. (The latency of onboard SRAM is always much better, though) \$\endgroup\$ – pjc50 Dec 5 '12 at 17:08
  • \$\begingroup\$ Another difference between SRAM and DRAM is the possible variability of latency. In addition to the column read or write command, a DRAM access may need a row activate command (if the accessed row is not the most recently used in its bank), and even a precharge command (if the old row has not been written back before a new row is to be activated). The refresh that DRAM requires can also interfere with ordinary accesses. Banking is used to provide better typical behavior, but the worst case--every access is to a different row in the same bank--can significantly affect performance. \$\endgroup\$ – Paul A. Clayton Dec 5 '12 at 23:52
  • \$\begingroup\$ This actually explains a lot for why many factors can affect the speed of memory intense program \$\endgroup\$ – Earlz Dec 6 '12 at 4:42
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    \$\begingroup\$ If you're using the onboard SRAM of an FPGA then that usually will do a write in one cycle and a read in two. Speed of PC L2/L3 cache isn't relevant. \$\endgroup\$ – pjc50 Dec 6 '12 at 10:19

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