I have the following dev FPGA board:

Altera Cyclone II EP2C5T144 FPGA Dev Board

This FPGA has a 50mhz clock. However I want to interface with an external FTDI device that runs at 60mhz. I am driving my VHDL process off the 60mhz clock as an input.

My question is can this safely work? I'm thinking its not safe because the FPGA flip flops are running at 50mhz but its being "forced" to run at 60mhz since the process is driven off this input clock pin?

Should I be removing the FPGA oscillator and connecting it to the existing FTDI oscillator? I'm still very new to this so sorry if this is really silly question :).

  • \$\begingroup\$ Useful search term "clock domain crossing". Avoid, and use a single clock if at all possible : for example run the whole lot off 60MHz and ignore the 50MHz input. \$\endgroup\$
    – user16324
    Jun 18, 2020 at 19:10
  • \$\begingroup\$ mhz = millihertz = 1 full cycle every thousand seconds. \$\endgroup\$
    – DKNguyen
    Jun 18, 2020 at 23:00
  • \$\begingroup\$ how would I run everything off the 60mhz? just physically connect the 60mhz clock in place of the current 50mhz so that both devices share the same clock inputs? \$\endgroup\$
    – paulm
    Jun 18, 2020 at 23:02

2 Answers 2


Most FPGAs have multiple clock capable pins, and you decide which one drives which registers (usually with some constraints, see your parts reference manual).

Just because you have a clock hooked to one of the clock capable pins does not mean you have to use it....

I would hook your 60MHz to a clock capable IO pin and then run all your logic off that clock and just ignore the 50Mhz one. Note that typically NOT all IO pins are clock capable but there are usually a few per IO bank that are (In various ways, again see the device manual), fpga clocking is usually slightly separate routing wise from the logic itself.

The reason to ignore the 50Mhz one is that due to something called metastability running signals between logic working at different clock frequencies is something of an advanced subject, not usually hard, just not something you need to be dealing with if clocking is still a mystery.

60MHz is basically DC in FPGA clock terms, but you do still need to define your clocks and constrain timing for the new rate. Unless you have a STUPID amount of combinatorial stuff between the registers, 60MHz is unlikely to cause you serious problems closing timing.

  • \$\begingroup\$ Thanks - I removed the 50mhz clock from the dev board and wired the FTDI 60mhz clock in its place, so now both devices run at the same clock and (probably?) without much skew \$\endgroup\$
    – paulm
    Jun 26, 2020 at 14:23
  • \$\begingroup\$ @paulm you could have generated a 60 MHz clock from the 50 MHz clock with one of the builtin PLLs. \$\endgroup\$ Sep 5, 2020 at 8:52
  • \$\begingroup\$ wouldn't that result in each 60Mhz clock not being in sync though? like the rise/fall edges don't match the same time step? \$\endgroup\$
    – paulm
    Sep 6, 2020 at 13:48

For Cyclone II you can easily apply a 60MHz clock input via the EXT_CLOCK SMA.

I take it this is what you are doing? Make sure you synthesize for this clock rate.

It is not the flops to worry about, but rather the combinational logic delays. The compiler will make sure that internal logic meets the delay requirements, and it will re-configure your logic to make it work. To understand this better, read up on "set-up and hold".

If you are using external memory, other restrictions apply as well, but with 60MHz you are well within the maximum.

Beware, you still have to meet the setup & hold timing conditions at your I/O, if you are running a synchronous interface. You'll need a scope to verify.

At 60MHz and short wires/traces there should be no issue, so you could be lucky without further testing, but I would not recommend you rely on luck.

I haven't used your board, but for a possible clock input see https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_cii_starter_board_rm.pdf

enter image description here

  • \$\begingroup\$ Where is the information about EXT_CLOCK SMA? I can't find it in cyc2_cii5v1.pdf? On the dev board there is only a 50mhz clock and so I am using the other devices clock as an input on a general I/O pin. Hence why I am quite confused about how they interact with each other. \$\endgroup\$
    – paulm
    Jun 18, 2020 at 23:01
  • \$\begingroup\$ @paulm I have added a pic and a link, but if the board doesn't have it, then the GPIO and connector will have to do. (The external clock input is a GPIO). In any case make sure you declare it as a clock and synthesize it at the right rate. \$\endgroup\$
    – P2000
    Jun 19, 2020 at 5:27
  • \$\begingroup\$ well the board has a 50mhz clock connected to pin 17. If I leave the other FPGA pins running off this 50mhz but disconnect pin 17 and reconnect it to the 60mhz would that work? What is the purpose of the other internal FPGA clock pins if they can't be used in a design? \$\endgroup\$
    – paulm
    Jun 19, 2020 at 12:57
  • \$\begingroup\$ @paulm You CAN use several clocks all together. Can you send a link to the board's manual? If it's Rio, I see the tech spec with 50MHz on-board xtal, but I can't locate a manual/schematic etc.. In general, you don't have to disconnect any pins, you can supply both clocks and select them internally. \$\endgroup\$
    – P2000
    Jun 20, 2020 at 0:06

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