Synchronous counter delay calculation

Question

My Doubt is that, This is synchronous counter, all the flip-flop are activated simultaneously Right?

Suppose at t=0 clock is activated then j0 and k0 will be activated instantly but my doubt is that in this time what will be the content of j1 and k1 or j2 and k2 does they have previous value i.e value they contain in previous clock cycle? Right? Okay now t=0 j0 and k0 will output qo complement this will reach AND gate and after 10 ns they will reach j1 and k1 right? Does my understanding is correct? Please help me to visualize how to calculate delay. Somewhere i read we taking only maximum delay I'm all confused here Please help.

Answer 1

My Doubt is that, This is synchronous counter, all the flip-flop are activated simultaneously Right?

Right

Suppose at t=0 clock is activated then j0 and k0 will be activated instantly but my doubt is that in this time what will be the content of j1 and k1 or j2 and k2 does they have previous value i.e value they contain in previous clock cycle?

if you mean t=0 when power is first applied, then the output is random (undetermined) depending on the race between the internal gates of the flip-flop. We can force the initial value by external components but it is not related to this question.

now t=0 j0 and k0 will output qo complement this will reach AND gate and after 10 ns they will reach j1 and k1 right?

Q0 will change on the clock positive edge and the output of the AND gate will be guarantied to be as expected after 10 ns and stable.

to find out the maximum clock frequency you must take into consideration that after any clock edge, the next clock edge must not arrive before all the AND outputs are stable including the last one although it does not affect the operation but at the end the output is here to be used (so after the input is stable and the output is stable on each one).