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I have a 50MHz 2ppm TCXO that I need level shifting from 1.8V to 3.3V. I looked for solutions here and decided to use a single IC solution rather than using a mosfets because I'm not confident enough to deal with EMI and noises from bad board layouts. So I was looking for solutions through various vendors and the slew rate seems to be the most important factor to be. since the clocks are coming directly from the oscillator, propagation delay isn't a big problem.

But I couldn't find the slew rate specs. for the IC's that I found. for example 2N7001T by TI fits my conditions, but what should I check to know that the slopes of the output clock is stiff as the input?

More easily put, how do I know if an IC can support 50MHz clock speed?

Edit

From the replies, I searched for buffer, driver ICs and found that on top of the level translation, Hysteresis is also important for the exact clock replication. So ended up with a Schmitt trigger buffer that had stability and short delay. SN74LVC1G17

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    \$\begingroup\$ A simple logic buffer should suffice (SN74LV1T34 does 1.8V->3.3V @50MHz). \$\endgroup\$
    – Tom Carpenter
    Commented Jun 19, 2020 at 10:17
  • \$\begingroup\$ Do you have a 3.3V rail available to power the level-shifting IC? Also, is it possible for the 1.8V to be present when 3.3V is absent? And relatedly, is it possible for 3.3V to be present when 1.8V is absent? \$\endgroup\$
    – user57037
    Commented Jun 20, 2020 at 9:17
  • \$\begingroup\$ You can use a level-shifting buffer or you can probably use a lvds receiver such as SN65LVDS2. Instead of feeding it a differential signal, you would set one of the inputs at 0.9V and drive the other input with the 1.8V clock output. \$\endgroup\$
    – user57037
    Commented Jun 20, 2020 at 9:32
  • \$\begingroup\$ Answers should not be provided in an edit, only accepting an answer leaves a question resolved. If what you did is different from.others suggestions post your own answer to accept. \$\endgroup\$
    – Chris Stratton
    Commented Jun 22, 2020 at 12:19

2 Answers 2

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If the edge speed is 10% of the period, that being 20 nanoseconds, then a 2 nanosecond edge speed up and 2 nanoSecond down seem good. That is 5v/2nS = 2.5 volts/nanosecond, into at least 20pF Cload.

And place a 0.1uf cap within 1mm of the VDDpin. Over a gnd plane, for low EMI and low jitter. You might even insert a series 1 ohm or 10 ohm resistor, between the cap/level-shifter and the other +5 loads, to better isolate the level-shifter current demands from other +5v demands.

Without some series impedance, your 0.1uf is being used to help provide the transient charge needs of all your other ICs on the +5 VDD trace,. So use the series impedance to reduce the effects of that copper trace.

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The site isn't for part recommendations, so I'm not posting this as a definitive answer but as guidance.

Search for a 'clock buffer' or 'clock driver' IC.

The part you list as an example is for data transfer.

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