I'm trying to switch the colors of a 4-bitmap image using VHDL . In a 4 bit-image . Which means we have these types of colors .

enter image description here

r_in : in std_logic_vector(7 downto 0);
g_in : in std_logic_vector(7 downto 0);
b_in : in std_logic_vector(7 downto 0);

r_out : out std_logic_vector(7 downto 0);
g_out : out std_logic_vector(7 downto 0);
b_out : out std_logic_vector(7 downto 0);

Assuming we have these vectors in the entity .

Is it possible check the color of the image using the Hexadecimal code ? for example :

if ( r_in = #16#AA0000 )
r_out <= #16##0000AA;
b_out <= #16#AA0000;

Something like that .

Otherwise what can I do instead ?

  • \$\begingroup\$ R_in can't be AA0000 because it's 8 bits and AA0000 is 24 bits \$\endgroup\$ – user253751 Jun 23 '20 at 12:38

You can represent hexadecimal literals for assignment or comparison with bit vectors of various types (like std_logic_vector) using a notation of the form x"ab12". For example:

if ( r_in =x"AA0000" ) then
  r_out <= x"0000AA";
  b_out <= x"AA0000";
end if;

For integers, you can use a notation like 16#ab12#, reference https://stackoverflow.com/questions/38777859/vhdl-using-hex-values-in-constants

  • \$\begingroup\$ Thank you .Should I leave the Input/Output vectors 8 bits (7 downto 0) ? \$\endgroup\$ – Gaston Jun 22 '20 at 15:38
  • 1
    \$\begingroup\$ That would be 16#ab12# \$\endgroup\$ – user_1818839 Jun 22 '20 at 16:06
  • \$\begingroup\$ Since your color is presented by three inputs,I think you need to concatenate the left hand side to match the color bit-width as if ( {r_in,g_in,b_in} = 0xXXXXXX ) then ... \$\endgroup\$ – Nazar Jun 22 '20 at 16:06
  • \$\begingroup\$ @Nazar I'm sorry but can you make a little example about your idea please \$\endgroup\$ – Gaston Jun 22 '20 at 18:55
  • 2
    \$\begingroup\$ In your question you have if ( r_in = #16#AA0000 ), where your left side is 8bit and the right side is 24bit. Unless you know what you are doing, that comparison does not make sense in general case. Therefore, the example that I gave you uses three 8-bit signals concatenated into 24bit so they match the width of the right hand side. I am not sure if that syntax is for VHDL, but I hope you get the point. \$\endgroup\$ – Nazar Jun 22 '20 at 22:57

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