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I'm trying to get the VGS of DMHC4035PMOS. Based on the simulation, I'm supposed to get -5.53V but I'm getting -8.2V on my PCB. Is there anything wrong with the design? What is the collector voltage of the current mirror on Q1 supposed to be?

DMHC4035 - H-bridge - https://www.diodes.com/assets/Datasheets/DMHC4035LSD.pdf

DMMT3904 - current mirror - https://www.diodes.com/assets/Datasheets/ds30311.pdf enter image description here

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  • \$\begingroup\$ 1) what is this circuit supposed to do? 2) Where does this circuit come from? 3) what is connected to the output? 4) include a link to the datasheet of the PMOS, "DMHC4035PMOS" means nothing to me. 4) What are DI_DMMT3904W? Are those 2N3904? In a simulator these transistors will match perfectly but on a PCB they will not. It is common practice to add resistors in series with the emitters to make the mirror copy the current more accurately. Why is that not done here? \$\endgroup\$ Jun 22, 2020 at 20:02
  • \$\begingroup\$ 5) It is quite easy to do some basic analysis on this circuit to determine what the currents and voltages should be. Have you done that? If no, why not? \$\endgroup\$ Jun 22, 2020 at 20:03
  • \$\begingroup\$ 1) It's supposed to drive the H-bridge. 2) It's from my project. 3) A load, can be resistive load or solenoid. 4) Yes. I didn't know to add the resistors in series. Do you mean to add a 10ohm resistor to each of the emitter? 5) Yes I did that but I got a different results on the PCB and I'm wondering why the big difference of ~-5V and ~-8V. \$\endgroup\$
    – cy1125
    Jun 22, 2020 at 20:08
  • \$\begingroup\$ And i edited the post and added the datasheets link \$\endgroup\$
    – cy1125
    Jun 22, 2020 at 20:27
  • \$\begingroup\$ As the current mirror is one chip, matching will be good so no need for emitter resistors. I think the current mirror overcomplicates things, I'd use an NMOS and make R1 a voltage divider to not exceed \$V_{GS,max}\$ of the PMOS. Now think, what could be causing a higher \$V_{GS}\$? What determines the \$V_{GS}\$? So what entity is obviously to small/large? How do the simulated and measured current and voltage values compare to your hand calculations? \$\endgroup\$ Jun 22, 2020 at 20:37

1 Answer 1

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\$\Delta\, V_\text{BE}=2\:\text{mV}\$ (worst case at room temp and at \$2\:\text{mA}\$ collector current) would mean saturation currents are within \$8\,\%\$ of each other. But another way of interpreting that same fact is that the collector currents are only guaranteed to be within \$8\,\%\$ of each other given the same \$V_\text{BE}\$. The sensitivity equation says that the effect is \$\% \,I_C = \frac{\Delta\,V_\text{BE}}{V_T}\$ and here that works out to \$\approx 7.7\,\%\$. I rounded that to \$8\,\%\$.

Adding another \$2\,\%\$ variation for the worst case variation in BJT \$\beta\$ means a total collector current matching of about \$10\,\%\$.

But this isn't everything. For example, a larger reason these BJTs are purchased is likely for current mirror usage. But do you notice that the datasheet specifies their matching at \$V_\text{CE}=5\:\text{V}\$ and that their matching over \$\beta\$ is specified for \$V_\text{CE}=1\:\text{V}\$? This brings up something else that's important to you for your configuration -- the Early Effect.

So, without imposing a circuit on these BJTs and without any consideration of the Early Effect, we already have a rough estimate about their collector current variations -- temperature being \$25\,^\circ\text{C}\$ and a \$2\:\text{mA}\$ collector current and some kind of \$V_\text{CE}\$ that is between \$1\:\text{V}\$ and \$5\:\text{V}\$, but we aren't exactly sure about that for now.

Let's just call it \$10\,\%\$ before the Early Effect.

What about the Early Effect?

Well, you've assigned \$\approx 1\:\text{mA}\$ as your set current with \$R_2\$. The model file you have (yes, I downloaded it) specifies that \$VA=114\:\text{V}\$. From this, we can estimate \$r_o=114\:\text{k}\Omega\$. In the case of \$Q_2\$, this means maybe an extra \$6\:\mu\text{A}\$ in its collector. Or, about \$6\,\%\$ more than expected. But for \$Q_1\$, where it appears you expect a collector voltage that is much higher -- perhaps about \$19\:\text{V}\$, this means about \$170\:\mu\text{A}\$ is added, instead. That's an extra \$17\,\%\$. The difference is at least another \$10\,\%\$. (Perhaps, if picky about it, another \$11\,\%\$.)

So now we are at about \$20\,\%\$ difference between their collector currents. Yes?

Is there more? Yes. We've failed to handle the above for worst-case behavior and we've just blindly applied two different effects. Let's combine them in a true worst-case combination and see where that goes.

Suppose \$Q_1\$'s saturation current is larger than for \$Q_2\$ by \$8\,\%\$. This means the \$V_\text{BE}\$ of \$Q_1\$ will want to be larger by \$2\:\text{mV}\$ for the same collector current. But sad to say, \$Q_2\$ presents a smaller \$V_\text{BE}\$. This smaller \$V_\text{BE}\$ means \$8\,\%\$ less collector current in \$Q_1\$. And that means a lower voltage drop across \$R_1\$. But that also means a higher collector voltage for \$Q_1\$. Which means more Early Effect current in \$Q_1\$.

If you work out the details (and I did, in equation form), then this means around \$\left[\left(100\,\%+8\,\%\right)^2-100\,\%\right]+10\,\%\approx 27\,\%\$ collector current difference between the two BJTs. (If you were picky before, add another \$1\,\%\$.)

That's the worst case, I think. It will probably be less than that. But that's how bad it can get without any emitter de-generation.

(The opposite take -- going the other way in the analysis -- results in about \$5\,\%\$ difference. So the reality is somewhere in the range between \$5\,\% \to 27\,\%\$, let's say. A span that exceeds \$20\,\%\$ over the entire range!)

In short, you may need emitter de-generation even with these devices.


There are other problems. While shared temperature from the calibrated value matters, for example, as it affects \$V_T\$. By itself, using the sensitivity equation, that can be important. But that's fixable with emitter de-generation. Perhaps the more important issue for your case may be the differential temperature. Note that the dissipation in \$Q_2\$ (diode-connected) is likely on the order of \$700\,\mu\text{A}\$ but that the dissipation in \$Q_2\$ is likely on the order of \$20\:\text{mW}\$. Basically, that is night and day between the two. So it is very likely that, unless you use very short narrow pulses to make your measurements, there will be a substantial thermal gradient across your internal BJT die. And that will add still more difference in behavior (which I have not bothered to analyze, yet.)

All this is reason why the 3-BJT and 4-BJT Wilson mirror was invented (I think.) Also, though, it's why emitter de-generation is important even with so-called matched BJTs.

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  • \$\begingroup\$ thanks for the reply! How do we determine the resistors value for the emitter de-generation? From my understanding, I just know that both values need to be matched but I'm not sure how to select the value. \$\endgroup\$
    – cy1125
    Jun 23, 2020 at 16:46
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    \$\begingroup\$ @cy1125 You have to decide on your goals, first. More de-generation provides better matching. But, at the very least, it costs you voltage headroom. There is no one size fits all answer to your question. As a general rule, you want to throw away at least \$5\,V_T\$, where you select the worst-case temperature you want to endure. But \$10\,V_T\$ is a lot better and \$50\,V_T\$ is nice to have, if you can have it. You also don't have the full topology for a good discrete version. I avoided discussing it, though. (Go here to see.) \$\endgroup\$
    – jonk
    Jun 23, 2020 at 16:54
  • \$\begingroup\$ I'm not sure about the VT. But the "+24" on my circuit is an adjustable source and it's range from "3.3V-24V". I'm thinking to add 50ohm resistors to both emitter of Q1 and Q2. On the spice simulation, it seems like the VGS still within the range of the PMOS but I'm just not sure if it'll be the same on the PCB itself. \$\endgroup\$
    – cy1125
    Jun 23, 2020 at 18:43
  • \$\begingroup\$ @cy1125 \$V_T\approx 28\:\text{mV}\$ at \$55\,^\circ\text{C}\$. So, with \$1\:\text{mA}\$ and my idea of nice goodness at "\$50\,V_T\$" you'd want about \$1.2\:\text{k}\Omega\$. That would be really nice. But it costs you \$1.2\:\text{V}\$ in overhead. But I also haven't seen your adjustable current source design. (I assume that just pasting a resistor isn't anyone's idea of "adjustable." So there must be more than you presented.) So it's hard to say what works for you. If you checked out my link, you'll see a precision adjustable current source. But it's two-quadrant -- tho can be adapted. \$\endgroup\$
    – jonk
    Jun 23, 2020 at 19:07
  • \$\begingroup\$ The "adjustable source" is basically having the "+24" on the schematic variable from 3.3V to 24V. So 3.3V could be at the source of R1 and the source pin of the PMOS at the same time. I tried to simulate with 1.2kohm but it won't actually work as if my source is 3.3V instead of 24V, my VGS at the gate would be -2.52V which might not close the PMOS gate fully. \$\endgroup\$
    – cy1125
    Jun 23, 2020 at 19:19

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