I have been given the task of designing a 12-bit pipelined adder:
There are 4-bit adders connected by latches. Why are latches used between the 4-bit adders? Is it for synchronization?
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The adder will have different inputs at each clock cycle. The output will appear two clock cycles later. You need all paths from input to output to have the same (cycle) delay so the outputs & intermediate results correspond.
It might help to draw a line through the corresponding latches to separate the 'time zones' as such.
Yes it is for synchronizing the carry from one 4 bit adder to the next.
The adder at the bottom performs addition of the lowest significant bits. The higher input bits are held in latches until the carry is ready for them at the next clock cycle.
The sum out of the lower bits is held until the sum of the higher bits are ready.
This technique is used if the adder word is too large (too wide) to complete an addition in one clock cycle.