I'm using TLC5945 LED driver. Microcontroller (I'm using LPC1343) must provide a clock for it's internal PWM timer/counter. Maximum allowed clock speed is specified as 30MHz.

I will have several boards with TLC5945 daisychained. Boards will be connected via board-to-board connectors or short ribbon cables, the width of one board is 10cm. I will have max 4 of them connected in series.

Probably I won't be using full 30MHz, but nevertheless I want to do it right - how do I route/condition the clock signal keeping it intact?

If I add a buffer like 74HC245 on the output of every board, I will get a 10ns delay after every buffer, I don't want that. Should I use specialized "zero delay" clock buffers? What kind of termination scheme should I employ?

  • 2
    \$\begingroup\$ A single cycle at 30MHz is ~33ns. Is being off by 1/3 of a single cycle per board that big of an issue? \$\endgroup\$ Dec 6, 2012 at 20:32
  • 1
    \$\begingroup\$ What a great question and answers. Every answer adds to the solution, without repeating any of the previous ones! \$\endgroup\$
    – Vorac
    Dec 7, 2012 at 14:07

3 Answers 3


30 MHz is enough that you do need to treat the signal as a transmission line problem. You'll need to pay attention to board layout across the design, including and especially at the connectors. You'll need to bring extra ground pins along with your 30 MHz signal, or possibly use special connectors.

You'll need information about the layout of your board, number of layers, and you may need to coordinate with your intended board manufacturer so that they can target a specific characteristic impedance for you, or just to get parameters such as dielectric constants.

It does sound like you're aware of many of these issues, but I thought it best to address them, because if you're not careful you may get a design that is functional but emits a lot of RF and will never get through an EMI test.

Guidelines for routing the signal:

  • Calculate the impedance and trace width.
  • Route your clocks first.
  • If possible, never route the signal through a via. If it must, put bypass capacitors near the via.
  • If possible/applicable, route the signal through an internal layer (so that outer ground and power planes can function as a sort of Faraday cage). In this case, the signal should be routed on one layer except for vias it needs to access chips.
  • The signal never goes anywhere without a ground plane (or strictly speaking, a reference plane).
  • The signal never crosses a boundary between power planes.
  • When going through a connector, surround it with grounds.
  • In a daisy chain, route directly to the clock inputs without using stubs, if possible. Diagram of daisy chain without stubs from Altera PDF
  • Cross other signals at a perpendicular.
  • If other signals must travel with it, give them clearance. Four-times the width of the trace.
  • Use parallel termination to ground with a resistance equal to the characteristic impedance of the microstrip/stripline, or source termination if the signal has only one destination. For a discussion see this related question.

Of course, in a real-world design, you might have to break some one of those guidelines.

Most of these rules follow from the observation that at high frequencies, the return current will try to travel close to the signal, so you must provide a path for the return current. If the return current is physically separated, you are creating a parasitic antenna. The ground (or power!) plane that provides a path for the return current is called the reference. Don't leave the reference plane. If you have to go through a via, the reference plane changes. The bypass capacitor is set between the new and old reference planes.

Your connectors will pose a problem, because they will likely have a different impedance from the PCB, so they will cause reflections and degrade the signal. One option may be to use an impedance controlled connector that matches the board impedance.

On the firmware side, you may need to experiment with drive strength to control the edge rate. Maximum drive strength is often the wrong answer. Your IC vendor should be able to provide an IBIS model, with which you can simulate the circuit to estimate signal integrity. Strictly speaking, it is not the clock frequency that causes signal integrity or EMC problems, but the edge rate (the time to transition between high and low) because fast edges manifest as broadband transients in the frequency domain. Reducing drive strength and/or slew rate will reduce the edge rate, and reduce harmonic emissions, while (probably) increasing clock jitter. Check the datasheets to see what the acceptable edge rate is for the clock's receivers.

My sense is that if you do your homework, you probably won't need any sort of signal repeater. Consider SCSI for example, which is a huge high speed parallel bus distributed over cables at around 100 MHz. If possible, consider investing in a program such as HyperLynx to simulate your layout.

Altera has an excellent guide for high speed routing issues.

  • \$\begingroup\$ Thanks for great insights. From your answer I get that there is no way I could pull this off with DIY etched boards? \$\endgroup\$
    – miceuz
    Dec 7, 2012 at 12:30
  • \$\begingroup\$ @miceuz: Well, if it's a hobby project then you're not as worried about EMC, so maybe. The consensus emerging is that this would be tricky for senior engineers to get right, and trying to do it DIY doesn't make anything easier. On the other hand, you can lower the clock frequency if it doesn't work out in this case. I'd try to find an alternate layout to reduce the length of the daisy chain. \$\endgroup\$
    – jbarlow
    Dec 7, 2012 at 21:31
  • \$\begingroup\$ Would upvote this twice if I could. \$\endgroup\$
    – Renan
    Dec 12, 2012 at 12:32

It's not going to hurt you to do all the things that jbarlow and David suggest, but let me try to make things a little bit easier for you (or maybe harder, because I'm going to say you can probably get away with a lot of things, but I'm not going to promise).

A classic rule of thumb is that you can consider a circuit to be a lumped circuit if none of it dimensions is longer than 1/10 the wavelength of the highest frequency signal of interest. If it's a lumped circuit you can consider your tracks as just connections between discrete elements. If its not a lumped circuit you need to worry about distributed circuit effects, and consider your traces as transmission lines.

You're talking about a clock frequency of 30 MHz, corresponding to a wavelength of 10 m. If propagating through FR4, this wavelength will be reduced to about 4.7 m. And a circuit length of 40 cm. So for the fundamental of the clock signal you're right on the edge of the old rule of thumb.

Problem: You don't just have to worry about the clock frequency, but how many harmonics of that frequency need to be transmitted to give the rise and fall time you want. If you deliberately slow down the edges you transmit you can probably get by with just the 1st and 3rd harmonics (David alluded to this when he mentioned not necessarily using maximum drive strength).

This gives you a maximum frequency of interest of 90 MHz, and corresponding wavelength (in FR4) of about 1.6 m. So the critical distance is 16 cm. That means that overall you want to provide a closely coupled return path, deisgn your tracks as transmission lines and terminate with an appropriate impedance, etc.

But you probably don't have to pay extra for controlled impedance. If you design with traces above the minimum width available from your vendor, (say 8 or 10 mil), the normal tolerances will most likely give you adequate performance.

And if along the way you have to go through a via, or run over a short gap in the ground plane, or you can't put a bypass capacitor right next to a load part, don't sweat it too hard. If you want to run your tracks straight from connector to connector, with a few cm stub to reach the load chips on each board, it'll be okay. If the length of the uncontrolled part of the path (or the slot in the ground plane) is less than a few cm, it's not going to ruin your day. Even if it's 10 cm, you're likely to get away with it, but don't push your luck.

For example, this means when you connect between boards, there's no need for a high-cost impedance-controlled connector. Even a couple of centimeters of ribbon cable will be fine. A ground-signal-ground or ground-signal-signal-ground pattern of wires in the ribbon is a good idea, but don't worry about impedance-matched twisted pair cables or coax.

For another, if you do decide to use a buffer on each board, that would enable you to pretty much treat the circuit on each board (at 10 cm length) as a lumped circuit. You will want to manage the buffer skew, as David described, and you'll have to limit the rise and fall times out of each buffer, but you'll gain a lot of flexibility in layout on each board without degrading functionality. That said, the more you do to keep your return paths close to your signal traces, the less likely you are to have a nasty surprise when it comes to EMC testing.


I think that @jbarlow's answer is fairly spot on. I want to add some to it, but I won't bother repeating what he has said.

The only thing that I would disagree with @jbarlow on is the use of repeaters, or buffering all of the signals. What he says is correct, "if you do your homework...". But that's the problem, doing your homework. You can do it, but you will need relatively expensive cables and connectors-- and then it'll only be "really difficult".

It does not appear that adding 10 ns delay to buffer the clock on each PCB is really a problem. It is hard for me to say for certain since you left out a lot of details about the other signals like BLANK and XLAT. But even if it is a problem, you can always buffer ALL signals. All gates in the 74xx245 will tend to have the same delay (or at least similar), and so the overall timing at the LED driver will remain good.

(Note: Check the datasheets. A good chip will list two different propagation delay numbers. One for an individual gate, and another showing the difference or skew in delay between gates within the same chip. Don't take my word for it. You will still need to do a proper timing analysis.)

Getting the termination and impedance of the signals between PCB's is critical to making this design work. Controlling impedance in multi-conductor cables is always difficult, and running a single signal through several PCB's and cables is just asking for trouble. You will have a change in impedance at many points along the signal length, which will create signal integrity problems. Buffering all of the signals between PCB's will help to manage this. At least the trace lengths and impedance changes on each signal will be kept to a minimum.

The use of zero delay buffers is not required, and could actually make things worse (and more expensive). Zero delay buffers are really Phase-Locked-Loops (PLL's) and require careful design to work perfectly. In most cases this isn't a big deal, but could certainly be a problem if your clock isn't perfect. It would be best to avoid these for this application. Additionally, a zero delay buffer is not suitable for buffering anything other than a continuously running clock-- so it doesn't help you to buffer any other signals.

  • \$\begingroup\$ Excellent points. I agree that the buffered signals approach is probably a lot safer and more likely to succeed. \$\endgroup\$
    – jbarlow
    Dec 7, 2012 at 6:24
  • \$\begingroup\$ How do I buffer ant terminate the signal? Is it MCU->Buffer->Series term->cable->Buffer->TLC5945->Buffer->series term->cable... or MCU->Buffer->Series term->cable->TLC5945->Buffer->series term->cable... ie do I need to buffer signals from both ends of cable or can I relay on buffer and termination to work both for connector/cable and for the board that comes next? \$\endgroup\$
    – miceuz
    Dec 7, 2012 at 12:41
  • \$\begingroup\$ @miceuz Ideally you would buffer it twice on each board. Once when the signal enters the board at one connector. Another time as the signal leaves the board at the other connector. Practically, doing it once is probably sufficient. So it would be MCU->Cable->LED->term->buf->cable->led->term->buf->cable->etc. Note that source-series-termination only works if you have a single load on the signal, which you do not. You have both an LED driver chip and a buffer. You should look at AC termination, which has a resistor and cap in series to ground at the far end. \$\endgroup\$
    – user3624
    Dec 7, 2012 at 15:04

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.