I am currently working on a design which requires me to design a module that combines 2 input streams of data & output it into a single output stream. To elaborate more, i can describe it with an example :
CLK Ip dword0 Ip dword1 Output 0 a b - 1 c d a 2 e f b 3 g h c 4 --- more data - d 5 --- ditto ----- e
So basically the output preserves the order of the inputs (input0 of the same clk followed by input1 & then move to the ip0 of the next clk). I know we need to stall the input stream at some point because the output rate is getting halved.
My idea so far: I was thinking of having the arbiter after the FIFO (so basically store the 2 input dwords into the FIFO, then keep popping the FIFO, store the rddata with dword0 & dword1 in a temp register & in a state-machine assign the dword 0 to output first & then in the next state assign the dword 1 to output. At this point assert the read en / pop the FIFO.
So, do you guys have any suggestions to improve the performance or do you see any issues with the plan so far ?
------ Added requirement ------ There's a 50% probability that some clk cycles, the input data stream is invalid. i.e. the valid could be set high for clk cycles 0,1 & invalid set to cycle 2 (so that input stream on clk 2 can be ignored). Hence, I added a FIFO so that I can go for the max number of cycles without stalling the input.