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I am currently working on a design which requires me to design a module that combines 2 input streams of data & output it into a single output stream. To elaborate more, i can describe it with an example :

 CLK Ip dword0  Ip dword1   Output  
  0       a        b          -  
  1       c        d          a  
  2       e        f          b  
  3       g        h          c  
  4   --- more data -         d  
  5   --- ditto -----         e

So basically the output preserves the order of the inputs (input0 of the same clk followed by input1 & then move to the ip0 of the next clk). I know we need to stall the input stream at some point because the output rate is getting halved.

My idea so far: I was thinking of having the arbiter after the FIFO (so basically store the 2 input dwords into the FIFO, then keep popping the FIFO, store the rddata with dword0 & dword1 in a temp register & in a state-machine assign the dword 0 to output first & then in the next state assign the dword 1 to output. At this point assert the read en / pop the FIFO.

So, do you guys have any suggestions to improve the performance or do you see any issues with the plan so far ?

------ Added requirement ------ There's a 50% probability that some clk cycles, the input data stream is invalid. i.e. the valid could be set high for clk cycles 0,1 & invalid set to cycle 2 (so that input stream on clk 2 can be ignored). Hence, I added a FIFO so that I can go for the max number of cycles without stalling the input.

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Since your FIFO can probably do only one input operation per clock cycle, then it makes sense to use a FIFO data width equal to your two dwords and input both dwords on each cycle.

On the reading side, I don't think you need a temp register for both dwords.

If you're using a FPGA then the FIFO generator provided by the manufacturer (example) should include an option to have different data widths for the input and output ports, which solves your problem.

If you want to write your own FIFO code then check if your dual port RAM has a "variable aspect ratio" option to get one dword on the output port and two dwords on the input port. If that's not available the simplest would be to use two RAM blocks (one per dword) and a mux to route the output of the correct RAM block to the output of the circuit, plus the usual FIFO code. Note the input pin of the mux which chooses which dword goes to the output is the lower address bit of the FIFO counter, so you probably don't need a state machine for that.

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If you can "stall the input" (your words), it isn't at all clear why you need a FIFO at all. Just stall the input on every other clock right from the beginning:

 CLK Ip dword0  Ip dword1   Output  
  0       a        b          -  
  1       -        -          a  
  2       c        d          b  
  3       -        -          c  
  4       e        f          d  
  5   ---  etc. -----         e

Now all you need is a register for each input and a mux.

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  • \$\begingroup\$ Ok, to clarify .. if you see the module input & output rates .. the input rate is 2 dwords /clk & output is 1 dword/clk, so there's no way even with a really deep FIFO, we can avoid the situation of taking a perf hit by not stalling the inputs. One of the requirements is that in some clk cycles, the input data stream can be ignored (valid set to 0). So, hence I added a FIFO -- to go for the max cycles without adding a FIFO. I'll add this requirement to the post. \$\endgroup\$ – rahdirs Jun 26 '20 at 2:34
  • \$\begingroup\$ So just add FIFO(s) upstream of this logic. It just needs to be big enough to handle the largest expected burst. But doesn't the fact that you can "stall the input" in the first place mean that there are already FIFOs there? You really need to be a lot more clear about what your actual requirements are. \$\endgroup\$ – Dave Tweed Jun 26 '20 at 3:39

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