Producing a VGA signal with an FPGA has been done by so many people it is a common starter project. What I cannot find is information on how to decode a VGA signal with a FPGA for example to capture a frame of video in memory. Assume there is nothing but R, G, B, VSYNC, HSYNC to work with, no DDC. Assume converting analog RGB to digital can be done.
VSYNC gives you the refresh rate and the number of HSYNCs between each gives you the number of lines. Let's say it is easy to count 525 lines and the refresh rate is 60Hz. That part is not hard.
How do you decide the number of pixels in each row and therefore the pixel clock? Is it a case of trying to fit various known values (from a table such as VGA Timing or the VESA DMT spec) based on the known information (lines, refresh) and just seeing what cases result in a HSYNC and front/back porch in expected places, giving a known pixel clock to use for sampling pixels?