Producing a VGA signal with an FPGA has been done by so many people it is a common starter project. What I cannot find is information on how to decode a VGA signal with a FPGA for example to capture a frame of video in memory. Assume there is nothing but R, G, B, VSYNC, HSYNC to work with, no DDC. Assume converting analog RGB to digital can be done.

VSYNC gives you the refresh rate and the number of HSYNCs between each gives you the number of lines. Let's say it is easy to count 525 lines and the refresh rate is 60Hz. That part is not hard.

How do you decide the number of pixels in each row and therefore the pixel clock? Is it a case of trying to fit various known values (from a table such as VGA Timing or the VESA DMT spec) based on the known information (lines, refresh) and just seeing what cases result in a HSYNC and front/back porch in expected places, giving a known pixel clock to use for sampling pixels?


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Digitizing of video is best done with a chip meant for that purpose. Many manufacturers have chips that contain triple video ADC. These take in the analog RGB and digital HS/VS syncs. They generate the pixel clock with a PLL based on the HS signal, based on how many pixels per line you want to have. So it is the job of the programmer to identify the video format it might be based on information given by the chip and configure the parameters so that you get the output you want for that format. The available detection parameters usually include lines per frame, sync polarities and some kind of way to know the HS or VS rate in some units. If there is no detection info available from the chip then MCU/FPGA needs to analyze the HS/VS sync signals itself.

So basically you could have a list of formats in a table. If you see that the video currently arriving matches some entry in the format table, then that format is coming in. Sure, you can use any method you want for detection, to support any formats you want.

For example, if you detect you have 525 HS pulses per VS pulse, the sync polarities are both negative pulses, and you either measure the VS to be close enough to 59.94 Hz, or HS is close enough to 31.46875 kHz, then that should be the format that needs 800 pixels per line to get the correct pixel clock of 25.175 MHz.

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    \$\begingroup\$ I'd also like to point out that the "classical" way of self-built frame grabbers to know which video format they're getting is simply specifying as few formats as possible in their EDID, so that the attached video-generating devices doesn't try anything funny. \$\endgroup\$ Jun 26, 2020 at 7:03
  • \$\begingroup\$ Thanks. I'm primarily interested in older VGA implementations where there is no EDID but I think it's going to be possible to pick the right mode from the range of possible modes. I assumed from the guessing and resync process monitors go through that it had to be something like that. \$\endgroup\$ Jun 27, 2020 at 0:26

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